參數(shù)資料
型號: MAX4356ECD+T
廠商: Maxim Integrated Products
文件頁數(shù): 21/41頁
文件大?。?/td> 0K
描述: IC VIDEO CROSSPOINT SWIT 128TQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 250
功能: 視頻交叉點開關(guān)
電路: 1 x 16:16
電壓電源: 單/雙電源
電壓 - 電源,單路/雙路(±): 5V,± 3 V ~ 5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-LQFP(14x20)
包裝: 帶卷 (TR)
MAX4356
16 x 16 Nonblocking Video Crosspoint Switch
with On-Screen Display Insertion and I/O Buffers
28
______________________________________________________________________________________
Pin Description
PIN
NAME
FUNCTION
1–4, 30–38, 103
N.C.
No Connection. Not internally connected. Connect to AGND.
5, 7, 9, 11, 13,
15, 17, 19, 21, 23,
25, 27, 121, 123,
125, 127
IN0–IN15
Buffered Analog Inputs
6, 8, 10, 12, 14,
16, 18, 20, 65, 66,
100, 101, 102,
120, 122, 124,
126
AGND
Analog Ground
22, 24, 26, 28
A3–A0
Address Programming Inputs. Connect to DGND or VDD to select the address for individual
output address mode. See Table 3.
29, 67, 71, 75, 79,
83, 87, 91, 95, 99
VCC
Positive Analog Supply. Bypass each pin with a 0.1
F capacitor to AGND. Connect a single
10
F capacitor from one VCC pin to AGND.
39
DOUT
Serial Data Output. In complete matrix mode, data is clocked through the 96-bit Matrix Control
Shift register. In individual output address mode, data at DIN passes directly to DOUT.
40
DGND
Digital Ground
41
AOUT
Address Recognition Output. AOUT drives low after successful chip address recognition.
42
SCLK
Serial Clock Input
43
CE
Clock Enable Input. Drive low to enable the serial data interface.
44
MODE
Serial Interface Mode Select Input. Drive high for complete matrix mode (mode 1), or drive low
for individual output address mode (mode 0).
45
RESET
Asynchronous Reset Input/Output. Drive RESET low to initiate hardware reset. All matrix
settings are set to power-up defaults and all analog outputs are disabled. Additional power-on
reset delay may be set by connecting a small capacitor from RESET to DGND.
46
UPDATE
Update Input. Drive UPDATE low to transfer data from Mode registers to the matrix switch.
47
DIN
Serial Data Input. Data is clocked in on the falling edge of SCLK.
48
VDD
Digital Logic Supply. Bypass VDD with a 0.1F capacitor DGND.
49–64
OSDKEY0–
OSDKEY15
Digital Control Input. Control for the fast 2:1 OSD insertion multiplexer routing signal to output
buffers. A logic high routes the programmed IN_ analog input signal to the output buffer. A
logic low routes the dedicated OSDFILL_ input to the corresponding output buffer.
68, 70, 72, 74, 76,
78, 80, 82, 84, 86,
88, 90, 92, 94, 96,
98
OUT0–
OUT15
Buffered Analog Outputs. Gain is individually programmable for AV = +1V/V or AV = +2V/V
through the serial interface. Outputs may be individually disabled (high impedance). On
power-up or assertion of RESET, all outputs are disabled.
69, 73, 77, 81, 85,
89, 93, 97, 128
VEE
Negative Analog Supply. Bypass each pin with a 0.1
F capacitor to AGND. Connect a single
10
F capacitor from one VEE pin to AGND.
104–119
OSDFILL0–
OSDFILL15
Dedicated OSD Analog Signal Buffered Inputs. For each output buffer amplifier OSDFILL, the
input signal is routed to output buffer amplifier OUT when the corresponding OSDKEY is low.
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