
M
Single/Dual/Quad, Micropower, Single-Supply,
Rail-to-Rail Op Amps
10
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Test Circuits/Timing Diagrams
V
IN
1V/div
200
μ
s/div
V
OUT
1V/div
V
CC
= 3V
V
EE
= 0
Figure 1. Rail-to-Rail Input and Output Operation
R1
V
OUT
R3 = R2 II R1
R3
V
IN
R2
MAX409_
Figure 2a. Reducing Offset Error Due to Bias Current: Inverting
Configuration
R3
VOUT
R3 = R2 II R1
VIN
R1
R2
MAX409_
Figure 2b. Reducing Offset Error Due to Bias Current:
Noninverting Configuration
1.7k
1.7k
TO INTERNAL
CIRCUITRY
TO INTERNAL
CIRCUITRY
IN–
IN+
MAX4091
MAX4092
MAX4094
Figure 3. Input Stage Protection Circuitry