參數(shù)資料
型號: MAX3996CGP
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 其它接口
英文描述: 3.0V to 5.5V, 2.5Gbps VCSEL and Laser Driver
中文描述: SPECIALTY INTERFACE CIRCUIT, CQCC20
封裝: 4 X 4 MM, 0.90 MM HEIGHT, QFN-20
文件頁數(shù): 3/17頁
文件大?。?/td> 785K
代理商: MAX3996CGP
M
3.0V to 5.5V, 2.5Gbps VCSEL
and Laser Driver
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 3.0V to 5.5V, T
A
= 0°C to +70°C, unless otherwise noted. Typical values are at V
CC
= 3.3V, TC pin not connected, T
A
=
+25°C.) (Figure 1)
PARAMETER
SYMBOL
CONDITIONS
Minimum Modulation Current
i
MOD
Maximum Modulation Current
i
MOD
R
L
25
Accuracy of Modulation Current
(Part-to-Part Variation)
(i
MOD
30mAp-p into 25
)
i
MOD
= 5mA into 25
, 20% to 80% (Note 3)
i
MOD
= 10mA into 25
, 20% to 80% (Note 3)
Edge Transition Time
t
r
, t
f
i
MOD
= 30mA into 25
, 20% to 80% (Note 3)
i
MOD
= 5mA into 25
(Notes 2, 3)
i
MOD
= 10mA into 25
(Notes 2, 3)
Deterministic Jitter
i
MOD
= 30mA into 25
(Notes 2, 3)
Random Jitter
(Note 3)
Modulation Current During Fault
i
MOD_OFF
Tempco = MAX, R
MOD
= open
Modulation Current Tempco
Tempco = MIN, R
TC
= open
Input Resistance
R
IN
Differential
Output Resistance
R
OUT
Single ended; outputs to V
CC
Input Common-Mode Voltage
SAFETY FEATURES
(See
Typical Operating Characteristics)
MIN
TYP
MAX
2
UNITS
mA
P-P
mA
P-P
30
40
R
MODSET
= 2.37k
-10
+10
%
54
55
65
17
14
9
2
15
4000
50
100
125
130
35
22
20
8
200
ps
ps
P-P
ps
RMS
μA
P-P
ppm/
°
C
85
42
115
58
V
50
V
CC
- 0.3
MODSET and TC Pin
Fault Threshold
200
mV
BIAS Pin Fault Threshold
A fault will be triggered if V
BIAS
is less than
this voltage
300
400
mV
Excessive Bias Current Fault
A fault will be triggered if V
MON2
exceeds
this voltage
400
440
mV
TX Disable Time
t_off
Time from rising edge of TX_DISABLE to
I
BIAS
= I
BIAS _OFF
and i
M OD
= i
M OD_OFF
( Note 3)
0.06
5
μs
TX Disable Negate Time
t_on
Time from falling edge of TX_DISABLE to
I
BIA S
and i
M OD
at 95% of stead y state ( N ote 3)
37
500
μs
Reset Initialization Time
t_init
Fr om p ow er ON or neg ation of FAU LT usi ng
TX _D S ABLE Ti me to set FAULT = l ow, i
M OD
=
95% of stead y state and I
BIAS
= 95% of steady
state ( N ote 3)
23
200
ms
Fault Assert Time
t_fault
Time from fault to FAULT = high, C
FAULT
< 20pF, R
FAULT
= 4.7k
(Note 3)
14
50
μs
TX_DISABLE Reset
t_reset
Time TX_DISABLE must be held high to
reset FAULT (Note 3)
0.01
1
μs
Note 1:
Supply current excludes bias and modulation currents.
Note 2:
Deterministic jitter is the peak-to-peak deviation from the ideal time crossings measured with a K28.5 bit pattern
00111110101100000101.
Note 3:
AC characteristics guaranteed by design and characterization.
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