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參數(shù)資料
| 型號(hào)： | MAX3992UTG+T |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 11/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DATA RECOVERY W/EQ 24-TQFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR） |
| PLL： | 是 |
| 主要目的： | SONET/SDH.XFP 光學(xué)接收器 |
| 輸入： | CML |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 693.5MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-WFQFN 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 24-TQFN-EP（4x4） |
| 包裝： | 帶卷 (TR) |
MAX3992
Detailed Description
The MAX3992 clock and data recovery with equalizer
recovers data from the XFI interface. It consists of an
equalizer with LOS power detector and a data retimer
with LOL indicator. An optional recovered clock may
also be enabled for performance testing.
Equalizer
The SDI inputs of the MAX3992 accept serial NRZ data
from XFI standard interfaces. When signals from
400mVP-P to 1000mVP-P are applied to a transmission
line from 0 to 12 inches of FR-4, the equalizer restores
them for recovery by the CDR. The equalizer removes
most of the deterministic jitter caused by frequency
dependent skin effect and dielectric losses, as well as
connector loss.
PLL Retimer
The integrated PLL recovers a synchronous clock that
is used to retime the input data. Connect a 0.047F
capacitor between CFIL and VCC to provide PLL damp-
ening. The external reference connected to REFCLK
aids in frequency acquisition. Because the reference
clock is only used for frequency acquisition, an
extremely low jitter generation can be achieved from a
low-quality reference clock. The reference clock should
be within ±100ppm of the bit rate divided by 16 or 64.
10Gbps Clock and Data Recovery
with Equalizer
8
_______________________________________________________________________________________
Figure 3. Functional Diagram
Functional Diagram
MAX3992
VTH
EQUALIZER
VCO
DFF
DQ
CML
PHASE/
FREQUENCY
DETECTOR
LOL
DETECTOR
LOS
LOL
FUNCTIONAL
CONTROL
CFIL
CML
SDI+
SDI-
REFCLK+
REFCLK-
SDO+
SDO-
SCLKO+
SCLKO-
FCTL1
FCTL2
PLL
200
POL
Pin Description (continued)
PIN
NAME
FUNCTION
22
REFCLK-
Negative Reference Clock Input, Digital. The REFCLK inputs are designed to be AC-coupled to the
reference clock source. REFCLK± have a 200
differential impedance. See the Detailed Description
section for more information. See Table 2.
23
FCTL1
Function Control Input 1, TTL. See Table 3 for more information.
24
VTH
LOS Threshold Input, Analog. A voltage applied to this input sets the LOS assert threshold. The LOS
power detector can be disabled if VTH is connected to VCC, which forces LOS low.
EP
Exposed
Pad
Supply Ground. The exposed pad must be soldered to the circuit-board ground for proper thermal
and electrical performance. The MAX3992 uses exposed-pad variation T2444-4 in the package
outline drawing. See the exposed-pad package.
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