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參數(shù)資料
| 型號： | MAX3969ETP+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 6/11頁 |
| 文件大小： | 0K |
| 描述： | IC AMP LIMIT 200MBPS 20-TQFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 類型： | 限幅放大器 |
| 應(yīng)用： | 光纖學(xué)網(wǎng)絡(luò) |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 20-TQFN-EP（4x4） |
| 包裝： | 帶卷 (TR) |
MAX3969
200Mbps SFP Limiting Amplifier
4
_______________________________________________________________________________________
10
μs/div
POWER-DETECT TIMING WITH SQUELCH
(INPUT = 12mVP-P, CFILTER = 0.01
μF,
R2 = 15k
Ω, 155Mbps, 223 - 1 PRBS)
IN
MAX3969 toc10
OUT
LOS
SD
PULSE-WIDTH DISTORTION
vs. DIFFERENTIAL INPUT VOLTAGE
MAX3969
toc11
DIFFERENTIAL INPUT VOLTAGE (mVP-P)
PULSE-WIDTH
DISTORTION
(ps)
1000
100
10
20
30
40
50
60
70
80
90
100
0
1
10,000
100Mbps
1-0 PATTERN
INPUT DATA THROUGH
117MHz FILTER
UNFILTERED
INPUT DATA
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
-40
-15
10
35
60
85
DATA OUTPUT TRANSITION TIME
vs. TEMPERATURE
MAX3969
toc12
AMBIENT TEMPERATURE (
°C)
TRANSITION
TIME
(ns)
Typical Operating Characteristics (continued)
(VCC = +3.3V, PECL outputs terminated with 50
Ω to VCC - 2V, R1 = 100kΩ, TA = +25°C, unless otherwise noted.)
Pin Description
PIN
NAME
FUNCTION
1
INV
Inverting Input of Internal Op Amp that Sets Power-Detect Threshold Voltage (Figure 1). Connect a
resistor from VTH to INV (R2), and from INV to ground (R1 = 100k
Ω), to program the desired threshold
voltage.
2
FILTER
Filter Output of Logarithmic Full-Wave Detectors (FWDs). The FWD outputs are summed together at
FILTER to generate the RSSI output. Connect a capacitor from FILTER to VCC for proper operation.
3
RSSI
Received-Signal-Strength Indicator Output. The voltage at RSSI indicates the input-signal power. The
RSSI output is reduced approximately 120mV when LOS is asserted.
4
IN-
Inverting Data Input
5
IN+
Noninverting Data Input
6 , 7, 8
GND
Ground
9
CZP
Autozero Capacitor Input. Connect a capacitor between CZP and CZN.
10
CZN
Autozero Capacitor Input. Connect a capacitor between CZP and CZN.
11
VCCO
Output-Buffer Supply Voltage. Connect to the same potential as VCC.
12
OUT+
Noninverting PECL Data Output. Terminate with 50
Ω to (VCC - 2V).
13
OUT-
Inverting PECL Data Output. Terminate with 50
Ω to (VCC - 2V).
14
SD
Signal Detect, PECL Output. The SD output is high when input power is above the power-detect
threshold, and low when input power is below the power-detect threshold. This pin is PECL-
compatible and should be terminated with 50
Ω to (VCC - 2V) or equivalent.
15
LOS
Loss-of-Signal Output, TTL Open Collector (with ESD Protection). The LOS output is high when input
power is below the power-detect threshold, and low when input power is above the power-detect
threshold.
16
LOS
Inverted Loss-of-Signal Output, TTL Open Collector (with ESD Protection). The LOS output is low
when input power is below the power-detect threshold, and high when input power is above the
power-detect threshold.
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