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參數(shù)資料
| 型號： | MAX3942ETG+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MODULATOR DRVR 10GBPS 24-TQFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 驅(qū)動器 |
| 驅(qū)動器/接收器數(shù)： | 1/0 |
| 電源電壓： | -5.5 V ~ -4.9 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 24-TQFN-EP（4x4） |
| 包裝： | 帶卷 (TR) |
MAX3942
10Gbps Modulator Driver
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(VEE = -5.5V to -4.9V, TA = -40°C to +85°C. Typical values are at VEE = -5.2V, IMOD = 100mA, and TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Off Current
MODEN = VEE, MODSET = VEE, DATA+ =
high, DATA- = low
1.6
mA
Differential Output Return Loss
RLOUT
IMOD = 50mA
10GHz
10
dB
Output Edge Speed
20% to 80% (Notes 6, 8)
23
32
ps
Setup/Hold Time
tSU, tHD
Figure 2 (Note 6)
25
ps
Pulse-Width Adjustment Range
(Notes 6, 8)
±30
±50
ps
Pulse-Width Control Input
Range (Single Ended)
For PWC+ and PWC-
VEE +
0.5
VEE +
1.5
V
Pulse-Width Control Input
Range (Differential)
(PWC+) - (PWC-)
-0.5
+0.5
V
Output Overshoot
(Notes 6, 8)
5
%
Driver Random Jitter
RJDR
(Note 6)
0.3
0.8
psRMS
Driver Deterministic Jitter
DJDR
PWC- = GND (Notes 6, 9)
8
13
psP-P
CONTROL INPUTS
Input High Voltage
VIH
(Note 10)
VEE +
2.0
V
Input Low Voltage
VIL
(Note 10)
VEE +
0.8
V
Input Current
(Note 10)
-80
+200
μA
Note 1: Supply current remains elevated once the retiming function has been enabled. Power must be cycled to reduce supply
current after the retiming function has been disabled.
Note 2: Power-supply noise rejection is specified as PSNR = 20Log(Vnoise (on Vcc) /
ΔVOUT). VOUT is the voltage across a 50Ω load.
Vnoise (on Vcc) = 100mVP-P.
Note 3: For DATA+, DATA-, CLK+, and CLK-.
Note 4: CLK input characterized at 10.7Gbps.
Note 5: Minimum voltage on OUT+ and OUT- is VEE + 1.9V.
Note 6: Guaranteed by design and characterization using the circuit shown in Figure 3.
Note 7: RMODEQV = (VMODSET - VEE) / (IMOD - 37mA).
Note 8: 50
Ω load, characterized at 10.7Gbps with a 1111 1111 0000 0000 pattern.
Note 9: Deterministic jitter is defined as the arithmetic sum of PWD (pulse-width distortion) and PDJ (pattern-dependent jitter).
Measured with a 10.7Gbps 27 - 1 PRBS pattern with 80 zeros and 80 ones inserted in the data pattern.
Note 10: For MODEN and PLRT.
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