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參數(shù)資料
| 型號： | MAX3877EHJ |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 2.5Gbps, +3.3V Clock and Data Retiming ICs with Vertical Threshold Adjust |
| 中文描述： | CLOCK RECOVERY CIRCUIT, PQFP32 |
| 封裝： | 5 X 5 MM, 1 MM HEIGHT, EXPOSED PAD, TQFP-32 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 550K |
| 代理商： | MAX3877EHJ |
M
2.5Gbps, +3.3V Clock and Data Retiming ICs
with Vertical Threshold Adjust
10
______________________________________________________________________________________
Phase Adjust
The internal clock is aligned to the center of the data
eye. For specific applications, this sampling position
can be shifted using the PHADJ input to optimize BER
performance. Refer to Figure 6 for setting the voltage at
PHADJ. When the phase adjust feature is not used,
PHADJ should be tied directly to V
CC
.
Loop Filter and VCO
The phase detector and frequency detector outputs are
summed into the loop filter. An external capacitor, C
F
,
is required to set the PLL damping ratio. Refer to
Design Procedure
for guidelines on selecting this
capacitor.
The loop filter output controls the on-chip LC VCO run-
ning at 2.488GHz. The VCO provides low phase noise
and is trimmed to the correct frequency. Clock jitter
generation is typically 1.2ps
RMS
within a jitter band-
width of 12kHz to 20MHz.
Loss-of-Lock Monitor
A loss-of-lock monitor is incorporated in the
MAX3877/MAX3878 frequency detector. When the PLL
is frequency locked, the internal
LOL
signal is high, and
if the PLL is out of frequency lock, the internal
LOL
sig-
nal immediately becomes low.
Loss-of-Signal Detector
A loss of signal detector is provided to detect a loss of
incoming data. If there are no transitions to the SDI
data input for approximately 1.65μs, the LOS signal
becomes high.
DC-Offset/Pulse-Width Distortion
Cancellation Loop
The input signal is first limited in the forward signal path.
The DC offset of this signal is detected and then amplified
in the feedback path. C
PWD
sets the cutoff frequency of
the low pass filter. This error signal is then subtracted
from the incoming data. When threshold adjust is
enabled, this loop acts as a pulse-width distortion cancel-
lation loop. Shorting the C
PWD
± pins together disables
the DC-offset/pulse-width distortion cancellation loop.
Threshold Adjust
This analog input controls the decision threshold of the
input stage. In applications where the noise density is not
balanced between logical zeros and ones (i.e., optical
amplification using EDFA amplifiers), it is possible to
achieve lower bit-error ratios (BER) by adjusting the input
threshold. Threshold adjust may be disabled by connect-
ing THADJ to V
CC
. The threshold level is set relative to
the center of the differential input voltage swing at the
input. Refer to Figures 3 and 7 for setting the voltage at
THADJ.
Input Select Pins
TTL inputs SIS and LREF are provided to select between
the SDI and SLBI inputs. Table 1 is a logical truth table
describing the operation of SIS and LREF. In this way,
the MAX3877/MAX3878 will automatically lock to the ref-
erence clock in the event of a loss-of-signal condition.
In systems where a valid clock output is required under
loss-of-signal conditions, a 155MHz reference clock is
applied to the SLBI inputs for holdover capabilities. This
holdover mode is activated with the LREF input. LREF
may be directly connected to the LOS pin or to an exter-
nal system loss-of-signal monitor.
Figure 6. Phase Alignment vs. PHADJ Voltage
100
50
0
-50
-100
0.2
1.2
0.7
1.7
2.2
PHASE ALIGNMENT vs. PHADJ VOLTAGE
PHADJ VOLTAGE
P
Figure 7. Threshold Level vs. THADJ Voltage
180
90
0
-90
-180
0.2
1.2
0.7
1.7
2.2
THRESHOLD LEVEL vs. V
TH
VOLTAGE
THADJ VOLTAGE
T
(
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX3877EHJ-T | 功能描述:計時器和支持產(chǎn)品 2.5Gbps 3.3V Clock & Data Retiming IC RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| MAX3877EVKIT | 功能描述:計時器和支持產(chǎn)品 Evaluation Kit for the MAX3877 MAX3878 RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| MAX3878E/D | 功能描述:計時器和支持產(chǎn)品 2.5Gbps +3.3V Clock and Data Retiming ICs with vertical Threshold Adjust RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| MAX3878EHJ | 功能描述:計時器和支持產(chǎn)品 2.5Gbps 3.3V Clock & Data Retiming IC RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| MAX3878EHJ-T | 功能描述:計時器和支持產(chǎn)品 2.5Gbps 3.3V Clock & Data Retiming IC RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
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