參數(shù)資料
型號: MAX3841
廠商: Maxim Integrated Products, Inc.
英文描述: Dual LVDS Transmitter/Receiver 16-TSSOP -40 to 85
中文描述: 12.5Gbps CML 2 x 2交叉點開關(guān)
文件頁數(shù): 4/8頁
文件大?。?/td> 290K
代理商: MAX3841
M
12.5Gbps CML 2
×
2 Crosspoint Switch
4
_______________________________________________________________________________________
Pin Description
PIN
1, 12
2, 5
3
4
6
7
8, 11
9
10
13, 24
14, 17
15
16
18
19
20, 23
21
22
NAME
V
CC
VCC1IN
IN1+
IN1-
SEL1
SEL2
VCC2IN
IN2+
IN2-
GND
VCC1OUT
OUT1-
OUT1+
ENO1
ENO2
VCC2OUT
OUT2-
OUT2+
FUNCTION
+3.3V Core Supply Voltage
Supply Voltage for CML Input IN1. Connect to 1.8V, 2.5V, or 3.3V.
Positive Serial Data Input 1, CML
Negative Serial Data Input 1, CML
Output 1 Select, LVCMOS Input. See Table 1.
Output 2 Select, LVCMOS Input. See Table 1.
Supply Voltage for CML Input IN2. Connect to 1.8V, 2.5V, or 3.3V.
Positive Serial Data Input 2, CML
Negative Serial Data Input 2, CML
Supply Ground
Supply Voltage for CML Output OUT1. Connect to 1.8V, 2.5V, or 3.3V.
Negative Serial Data Output 1, CML
Positive Serial Data Output 1, CML
Output 1 Enable, LVCMOS Input. See Table 1.
Output 2 Enable, LVCMOS Input. See Table 1.
Supply Voltage for CML Output OUT2. Connect to 1.8V, 2.5V, or 3.3V.
Negative Serial Data Output 2, CML
Positive Serial Data Output 2, CML
EP
Exposed Pad
Ground. The exposed pad must be soldered to the circuit board ground for proper thermal and
electrical performance.
Detailed Description
The MAX3841 contains a pair of CML inputs that drive
two 2:1 multiplexers, with separate select inputs SEL1
and SEL2, providing a 2
×
2 crosspoint data path. The
outputs of the multiplexers each drive a high-perfor-
mance CML output that can be disabled (powered
down) using the ENO1/ENO2 inputs. All of the data
paths are fully differential to minimize jitter, crosstalk,
and signal skew. See Figure 1 for the functional diagram.
CML Input and Output Buffers
The MAX3841 input and output buffers are terminated
with 50
to independent supply lines, and are also com-
patible with 100
differential terminations. (See Figures 3
and 4.) Separate power-supply connections are provided
for the core, input buffers, and output buffers to allow DC-
coupling to 1.8V, 2.5V, or 3.3V CML ICs. If desired, the
CML inputs and outputs can be AC-coupled.
The CML inputs accept serial NRZ data with differential
amplitude from 150mV
P-P
to 1200mV
P-P
(see Figure 2).
The CML outputs provide 500mV
P-P
nominal differential
swing, resulting in low power consumption.
MAX3841
CML
CML
CML
CML
1
0
1
0
OUT1
ENO1
SEL1
OUT2
ENO2
SEL2
IN1
IN2
2
2
2
2
Figure 1. Functional Diagram
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