參數(shù)資料
型號: MAX3840
廠商: Maxim Integrated Products, Inc.
英文描述: Dual LVDS Transmitter/Receiver 16-TSSOP -40 to 85
中文描述: +3.3V、2.7Gbps雙路2 x 2交叉點開關
文件頁數(shù): 6/10頁
文件大?。?/td> 388K
代理商: MAX3840
M
+3.3V, 2.7Gbps Dual 2
2 Crosspoint Switch
6
_______________________________________________________________________________________
_______________ Detailed Description
The block diagram in Figure 1 shows the MAX3840
architecture. The SELA_ and SELB_ pins control the rout-
ing of the signals through the crosspoint switch. Each
output of the crosspoint switch drives a CML output dri-
ver. Each of the outputs, DOA_ and DOB_, is enabled or
disabled by the respective ENA_ and ENB_ pins.
CML Inputs and Outputs
CML is used to simplify high-speed interfacing. On-
chip input and output terminations minimize the number
of external components required while improving signal
integrity. The CML output signal swing is small, result-
ing in lower power consumption. The internal 50
input
and output terminations minimize reflections and elimi-
nate the need for external terminations.
ROUTING CONTROLS
SELA0/SELB0
0
0
1
1
X
OUTPUT CONTROLS
ENA0/ENA1
1
1
1
1
0
OUTPUT SIGNALS
SELA1/SELB1
0
1
0
1
X
ENB0/ENB1
1
1
1
1
0
Signal at DOA0/DOB0
DIA0/DIB0
DIA0/DIB0
DIA1/DIB1
DIA1/DIB1
Power Down
Signal at DOA1/DOB1
DIA0/DIB0
DIA1/DIB1
DIA0/DIB0
DIA1/DIB1
Power Down
Table 1. Output Routing
DOA0+
0
1
0
1
DOA0-
ENA0
SELA0
CML
CML
DOA1+
DIA0-
DIA0+
DOA1-
ENA1
SELA1
CML
DIA1-
DIA1+
DOB0+
0
1
0
1
DOB0-
ENB0
SELB0
CML
DOB1+
DIB0-
DIB0+
DOB1-
ENB1
SELB1
CML
DIB1-
DIB1+
CML
CML
CML
320mV MIN
CML+
CML-
(CML+) - (CML-)
500mV
MAX
1000mV
MAX
640mV
MIN
Figure 1. Functional Block Diagram
Figure 2. CML Output Levels
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