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參數(shù)資料
| 型號(hào)： | MAX3831UCB |
| 廠(chǎng)商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類(lèi)： | 數(shù)字傳輸電路 |
| 英文描述： | +3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator |
| 中文描述： | MUX/DEMUX, PQFP64 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, MO-136AJ, TQFP-64 |
| 文件頁(yè)數(shù)： | 10/16頁(yè) |
| 文件大?。?/td> | 285K |
| 代理商： | MAX3831UCB |
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M
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
10
______________________________________________________________________________________
clock cycle between each channel. In this test mode, ser-
ial data is internally looped back to the demux. All frame
detect logic is exercised using this mode. The CML
inputs (SDI± and SCLKI±) and LVDS inputs (PDI_±) are
ignored in this mode. After the BIST mode is enabled, the
loss-of-frame flag
LOF
goes high, indicating that the self-
test has passed. In normal operation,
TEST
is left open
(internally pulled high), disabling the pattern generator
and accepting data from the parallel input channels.
Test Loopbacks
Two additional test loopbacks are provided: parallel
system loopback and serial line loopback.
Parallel System Loopback
In parallel system loopback, four 622Mbps parallel
input channels are phase aligned by an associated 10-
bit elastic store and routed to the output LVDS buffers.
This loopback is controlled by setting
PLBEN
low.
Normal data transmission is resumed when
PLBEN
goes high (internally pulled high).
Serial Line Loopback
Serial line loopback is used for testing the performance
of the optical transceiver and the transmission link. The
received 2.488Gbps data stream is routed to the trans-
mit CML output buffer. Line loopback is enabled when
LBEN
is asserted low. When
LBEN
is left open (internally
pulled high), normal serial-data transmission resumes.
LVDS Parallel Interface
The MAX3831 parallel interface includes four OC-12
data inputs, a 155MHz reference clock input, four
622Mbps parallel-data outputs, and a 622MHz parallel-
clock output (MAX3832, f
PCLKO
= 155MHz). All parallel
inputs and outputs are LVDS compatible to minimize
power dissipation, speed transition time, and improve
noise immunity. The 155MHz input signal at RCLKI
requires a duty cycle between 40% and 60%.
The LVDS outputs go into a high-impedance state when
TRIEN
is forced low. This simplifies system checks by
allowing vectors to be forced on the LVDS outputs.
CML Serial Interface
The MAX3831/MAX3832 provide a 2.488Gbps serial-
data stream to a driver and accept 2.488Gbps serial
data and a 2.488GHz clock signal from an external
clock and data recovery device (MAX3876). The high-
speed interface is CML compatible, resulting in lower
system power dissipation and excellent performance
(Figure 7).
__________Applications Information
Low-Voltage Differential
Signal Inputs/Outputs
The MAX3831/MAX3832 have LVDS inputs and outputs
for interfacing with high-speed digital circuitry. All LVDS
inputs and outputs are compatible with the IEEE-1596.3
LVDS specification. This technology uses 250mV to
400mV differential low-voltage amplitudes to achieve
fast transition times, minimize power dissipation, and
improve noise immunity.
For proper operation, the parallel clock and data LVDS
outputs (PCLKO+, PCLKO-, PDO_+, PDO_-) require
100
differential DC termination between the inverting
and noninverting outputs. Do not terminate these out-
puts to ground. The parallel-data LVDS inputs (PDI_+,
PDI_-) are internally terminated with 100
differential
input resistance and therefore do not require external
termination.
Interfacing with PECL/ECL
Input Levels
When interfacing with differential PECL input levels, it is
important to attenuate the signal while still maintaining
50
termination (Figures 8 and 9). Observe the com-
mon-mode input voltage specifications. AC-coupling is
required if a V
CC
other than 3.3V is used to maintain the
input common-mode level (Figure 8).
MAX3831
MAX3832
MAX3876
50
50
50
50
V
CC
V
CC
SDI+
SDI-
SDO+
SDO-
Figure 7. CML-to-CML Interface
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX3832UCB | Dual LVDS Transmitter/Receiver 16-SOIC -40 to 85 |
| MAX3841 | Dual LVDS Transmitter/Receiver 16-TSSOP -40 to 85 |
| MAX3841ETG | Dual LVDS Transmitter/Receiver 16-TSSOP -40 to 85 |
| MAX385EJE | Precision, Low-Voltage Analog Switches |
| MAX381EJE | Precision, Low-Voltage Analog Switches |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX3831UCB-D | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線(xiàn)路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| MAX3831UCB-TD | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線(xiàn)路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| MAX3832EVKIT | 功能描述:其他開(kāi)發(fā)工具 RoHS:否 制造商:Parallax 產(chǎn)品:ELEV-8 Hex Upgrade Kits 類(lèi)型:Robotics 工具用于評(píng)估:ELEV-8 Quadcopter 工作電源電壓: |
| MAX3832UCB | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| MAX3832UCB-D | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 3.3V 2.5Gbps SDH SONET MUX/DEMUX RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線(xiàn)路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
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