參數(shù)資料
型號(hào): MAX3815ACCM+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 9/11頁(yè)
文件大?。?/td> 0K
描述: IC DGTL VIDEO EQUALIZER 48TQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,000
類型: 視頻均衡器
應(yīng)用: HDMI,DVI,接收器
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-TQFP 裸露焊盤(7x7)
包裝: 帶卷 (TR)
_______________________________________________________________________________________ 7
MAX3815A
TMDS Digital Video Equalizer for
HDMI/DVI Cables
Detailed Description
The MAX3815A TMDS equalizer accepts differential
CML input data at rates of 250Mbps up to 2.25Gbps
(individual channel data rate). It automatically adjusts
to skin-effect losses in copper cable. It consists of four
CML input buffers, a loss-of-clock signal detector, three
independent adaptive equalizers, four limiting amplifiers,
and four output buffers (Figure 1).
CML Input Buffers and Output Drivers
The input buffers and the output drivers are implemented
using current-mode logic (CML) (see Figures 4 and 5). The
output drivers are open-collector and can be turned off
with the OUTON pin. The OUTLEVEL pin sets the output
drive current to one of three levels; see the Applications
Information and Pin Description sections for more infor-
mation. For details on interfacing with CML, refer to
Application Note 291: HFAN-01.0: Introduction to LVDS,
PECL, and CML.
Loss-of-Clock Signal Detector
The loss-of-clock signal detector indicates a loss-of-
clock signal at the CLKLOS pin. This is an open-collector
output that must be connected to VCC through a 4.7kω
external pullup. This resistor is required whether or not
the LOS output is used.
Adaptive Equalizer
The three data channels each contain an independent
adaptive equalizer. Each channel analyzes the incom-
ing signal and determines the amount of equalization to
apply.
Limiting Amplifier
The limiting amplifier amplifies the signal from the adap-
tive equalizer and truncates the top and bottom of the
waveform to provide a clean high- and low-level signal
to the output drivers.
Figure 1. Functional Diagram
INPUT
BUFFER
DRIVER
ADAPTIVE
EQ
LIMITING
AMPLIFIER
TERMINATED
3.3V CML
INPUT
BUFFER
DRIVER
ADAPTIVE
EQ
LIMITING
AMPLIFIER
TERMINATED
3.3V CML
INPUT
BUFFER
DRIVER
ADAPTIVE
EQ
LIMITING
AMPLIFIER
TERMINATED
3.3V CML
INPUT
BUFFER
DRIVER
LIMITING
AMPLIFIER
TERMINATED
3.3V CML
RXC_OUT+/-
OUTLEVEL
RX2_OUT+/-
RX1_OUT+/-
RX0_OUT+/-
RX0_IN+/-
RX1_IN+/-
RX2_IN+/-
RXC_IN+/-
CLKLOS
EQCONTROL
OUTON
CLOCK LOS
DETECTOR
MAX3815A
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