參數(shù)資料
型號(hào): MAX3804ETE
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi): 通信及網(wǎng)絡(luò)
英文描述: 12.5Gbps Settable Receive Equalizer
中文描述: SPECIALTY TELECOM CIRCUIT, QCC16
封裝: 3 X 3 MM, 0.80 MM HEIGHT, MO-220, TQFN-16
文件頁(yè)數(shù): 5/9頁(yè)
文件大小: 1525K
代理商: MAX3804ETE
M
12.5Gbps Settable Receive Equalizer
_______________________________________________________________________________________
5
Pin Description
PIN
NAME
FUNCTION
1, 4
V
CC1
CML Input Supply Voltage. Connect to +1.8V to +3.3V for DC-coupled CML. Input can also be
AC-coupled.
2
3
5
6
7
SDI+
SDI-
EQ1
EQ2
EQ3
GND
Positive Serial Data Input, CML
Negative Serial Data Input, CML
Equalizer Boost Control Logic Input LSB, LVTTL. See Table 1.
Equalizer Boost Control Logic Input, LVTTL. See Table 1.
Equalizer Boost Control Logic Input MSB, LVTTL. See Table 1.
Supply Ground
8, 16
9, 12
V
CC2
CML Output Supply Voltage. Connect to +1.8V to +3.3V for DC-coupled CML. Output can also be
AC-coupled.
10
11
SDO-
SDO+
N.C.
V
CC
Negative Serial Data Output, CML
Positive Serial Data Output, CML
No Connection. Leave unconnected.
+3.3V Core Supply Voltage
13, 14
15
EP
Exposed Pad
Ground. Must be soldered to the circuit board ground for proper thermal and electrical performance
(see the
Package and Layout Considerations
section).
Detailed Description
General Theory of Operation
The MAX3804
s low-noise linear input stage includes
two amplifiers, one with flat-frequency response, and
one with response that compensates for the loss
characteristic of an FR-4 PC board transmission line.
A current-steering network allows the designer to
control the amount of equalization to match the path
loss for specific applications. This network consists of a
pair of variable attenuators feeding into a summing
node. Equalization is set by a 3-bit LVTTL-compatible
input (EQ3, EQ2, and EQ1). By employing fixed control
of the equalization level, the MAX3804 provides optimal
performance for a specific path loss. A high-speed
limiting amplifier follows the equalizer circuitry to shape
the output signal (see Figure 1).
CML Input and Output Buffers
The MAX3804 input and output CML buffers are termi-
nated with 50
to V
CC1
and V
CC2
, respectively. The
equivalent circuit for the output is shown in Figure 2.
Separate supply voltage connections are provided for
the core (V
CC
), input (V
CC1
), and output (V
CC2
) circuit-
ry to control noise coupling, and to allow DC-coupling
to +1.8V, +2.5V, or +3.3V CML ICs. The CML inputs
and outputs can also be AC-coupled.
Use AC-coupling for single-ended cable applications.
The unused CML input must be connected through an
AC-coupling capacitor to a 50
termination.
The low-frequency cutoff of the input-stage offset-can-
cellation circuit is nominally 21kHz.
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