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參數(shù)資料
| 型號： | MAX3804 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 12.5Gbps Settable Receive Equalizer |
| 中文描述： | 12.5Gbps可設(shè)置接收均衡器 |
| 文件頁數(shù)： | 2/9頁 |
| 文件大?。?/td> | 1525K |
| 代理商： | MAX3804 |
M
12.5Gbps Settable Receive Equalizer
2
_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V
CC
)............................................-0.5V to +4.0V
CML Supply Voltage (V
CC1
, V
CC2
) ............-0.5V to (V
CC
+ 0.5V)
Current at Serial Output (SDO+, SDO-)............................
±
25mA
Input Voltage (SDI+, SDI-, EQ1,
EQ2, EQ3) ..............................................-0.5V to (V
CC
+ 0.5V)
ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, V
CC1
= V
CC2
= +1.65V to +3.6V, T
A
= -40°C to +85°C. Typical values are at V
CC
= V
CC1
= V
CC2
= +3.3V,
and T
A
= +25°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Continuous Power Dissipation (T
A
= +85°C)
16-Lead Thin QFN-EP (derate 17.5mW/
°
C
above +85°C) ........................................................1398mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-55°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETER
SYMBOL
I
CC
V
IN
CONDITIONS
MIN
TYP
35
MAX
50
1200
UNITS
mA
mV
P-P
Supply Current
CML Input Differential
AC-coupled or DC-coupled (Note 1)
400
CML Input Common Mode
DC-coupled
V
CC1
- 0.4
V
CC1
+ 0.1
V
CML Input Termination
CML Input Return Loss
CML Output Differential
CML Output Impedance
CML Output Transition Time
Single ended
Up to 5GHz
42.5
50
10
500
50
57.5
dB
V
OUT
400
42.5
600
57.5
35
30
30
+30
0.8
mV
P-P
ps
Single ended
20% to 80% (Notes 2, 6)
At 10.7Gbps (Notes 3, 4, 5, 6)
At 12.5Gbps (Notes 3, 4, 5, 6)
t
R
, t
F
24
17
Residual Jitter Output
(Total RJ, PWD, and PDJ)
ps
P-P
LVTTL Input Current
LVTTL Input Low
LVTTL Input High
I
IH
, I
IL
V
IL
V
IH
-30
μA
V
V
2.0
Note 1:
Differential Input Sensitivity is defined at the input to a transmission line. The transmission line is differential Z
0
= 100
, 6-mil
microstrip in FR-4,
ε
r
= 4.5, and tan
δ
= 0.02, V
IN
= (SDI+ - SDI-).
Note 2:
Measured with 0000011111 pattern at 12.5Gbps.
Note 3:
Residual jitter is the difference in total jitter (RJ, PWD, and PDJ) between the transmitted signal (at the input to the transmis-
sion line) and equalizer output. Total residual jitter is DJ
P-P
+ 14.2 x RJ
RMS
.
Note 4:
Measured at 10.7Gbps using a pattern of 100 ones, 2
7
PRBS, 100 zeros, 2
7
PRBS, and at 12.5Gbps using a K28.5 pattern.
Deterministic jitter at the input is from frequency-dependent, media-induced loss only.
Note 5:
V
IN
= 400mV
P-P
to 1200mV
P-P
, input path is 0 to 30in, 6-mil microstrip in FR-4,
ε
r
= 4.5, and tan
δ
= 0.02.
Note 6:
Guaranteed by design and characterization.
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