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參數(shù)資料
| 型號(hào)： | MAX3800UTJ+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 10/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC EQUALIZER DRVR 3.2GBPS 32TQFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 驅(qū)動(dòng)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 1/0 |
| 電源電壓： | 3.14 V ~ 3.46 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-TQFN-EP（5x5） |
| 包裝： | 帶卷 (TR) |
Detailed Description
The MAX3800 consists of a cable driver (transmitter)
and an adaptive cable equalizer (receiver). The driver
and equalizer are implemented on the same chip, but
they are completely independent.
The Cable Driver
The cable driver accepts differential or single-ended
current-mode logic (CML) input data at rates up to
3.2Gbps. The driver output is also implemented using
CML. The maximum output amplitude can be adjusted
over a typical range of 450mV to 870mV by changing
the value of the RMOD resistor between 10k
and
20k
(this resistor is connected between the RMOD pin
and ground).
The Adaptive Cable Equalizer
The adaptive cable equalizer accepts differential CML
input data at rates up to 3.2Gbps and is capable of
equalizing differential or single-ended signals. It auto-
matically adjusts to attenuation levels of up to 30dB at
1.6GHz (due to skin-effect losses in copper cable). The
equalizer consists of a CML input buffer, a loss-of-sig-
nal detector, a flat response amplifier, a skin-effect
compensation amplifier, a current-steering network, a
dual power-detector feedback loop, an output limiting
amplifier, and a CML output buffer (Figure 1).
General Theory of Operation
The shape of the power spectrum of a random bit
stream can be described by the square of the sinc
function, where sinc f = (sin
πf) / πf. For sufficiently long
bit patterns (nonrandom bit streams), sinc2(f) is a good
approximation. From the shape of the sinc2(f) function,
we can estimate the ratio of the power densities at any
two frequencies. The MAX3800 adaptive equalizer
employs this principle by incorporating a feedback loop
that continuously monitors the power at two frequencies
and dynamically adjusts the equalizer to maintain the
correct power ratio.
CML Input and Output Buffers
The input and output buffers are implemented using
current-mode logic (CML). Equivalent circuits are
shown in Figures 2 and 3. For details on interfacing with
MAX3800
3.2Gbps Adaptive Equalizer
and Cable Driver
6
_______________________________________________________________________________________
PIN
NAME
FUNCTION
1, 3, 6, 11, 14
VCCE
Equalizer Power Supply
2, 7, 10, 15,
23, 24, 26, 31
GND
Ground
4
EIN+
Positive Equalizer Input, CML
5
EIN-
Negative Equalizer Input, CML
8
CIM-
Negative Cable Integrity Monitor (CIM) Output
9
CIM+
Positive Cable Integrity Monitor (CIM) Output
12
EOUT-
Negative Equalizer Output, CML
13
EOUT+
Positive Equalizer Output, CML
16, 17
N.C.
No Connection. Leave unconnected.
18
LOS
Equalizer Loss-of-Signal Output, Active-Low
19, 22, 27,
30, 32
VCCD
Driver Power Supply
20
DIN+
Positive Driver Input, CML
21
DIN-
Negative Driver Input, CML
25
RMOD
Driver Output Modulation Adjust. A resistor connected from this pin to GND controls driver output
voltage.
28
DOUT+
Positive Driver Output, CML
29
DOUT-
Negative Driver Output, CML
EP
Exposed
Pad
Ground. The exposed pad must be soldered to the circuit board ground plane for proper thermal
and electrical performance.
Pin Description
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