參數(shù)資料
型號: MAX3784AUTE+T
廠商: Maxim Integrated Products
文件頁數(shù): 5/7頁
文件大小: 0K
描述: IC BOARD EQUALIZER 5GBPS 16-TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
應(yīng)用: 數(shù)據(jù)傳輸
電源電壓: 3 V ~ 3.6 V
封裝/外殼: 16-WQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 16-TQFN-EP(4x4)
包裝: 帶卷 (TR)
安裝類型: 表面貼裝
Detailed Description
General Theory of Operation
The MAX3784/MAX3784A adaptive equalizers extend
the reach of transmission lines in high-frequency back-
plane interconnect applications. They can be used for
4.25Gbps Fibre Channel, 4x 1.25Gbps Ethernet (5Gbps)
and other NRZ, 8b10b or short (
≤ 20 bits) CID data
types. Internally, the MAX3784/MAX3784A are com-
prised of an equalizer control loop and limiting output
driver. The equalizer block reduces intersymbol interfer-
ence (ISI), compensating for frequency-dependent
media-induced loss. The equalization control detects the
spectral contents of the input signal and provides a con-
trol voltage to the equalizer core, adapting it to different
media. The equalizer operation is optimized for short-run,
DC-balanced transmission codes.
Standby Mode
Standby saves power when the equalizer is not in use.
The EN logic input must be set high or open for normal
operation. Logic low at EN forces the equalizer into the
standby state.
CML Input and Output Buffers
The input and output buffers are implemented using cur-
rent-mode logic (CML). Equivalent circuits are shown in
Figures 3 and 4. For details on interfacing with CML,
refer to Maxim Application Note HFAN-01.0:
Introduction
to LVDS, PECL, and CML. The common-mode voltage
of the input and output is above +2.5V. AC-coupling
capacitors are required when interfacing this part with
devices terminated in voltages such as +1.8V. Values of
0.10F or greater are recommended.
MAX3784/MAX3784A
5Gbps PCB Equalizer
_______________________________________________________________________________________________________
5
Pin Description
PIN
NAME
FUNCTION
1, 7, 12
VCC
+3.3V Supply Voltage
2
IN+
Positive Input, CML
3
IN-
Negative Input, CML
4, 6, 9
GND
Supply Ground
5, 8, 14, 15,
16
N.C.
No Connection. Leave unconnected.
10
OUT-
Negative Output, CML
11
OUT+
Positive Output, CML
13
EN
Enable Equalizer. A logic high or open selects normal operation. A logic low selects low-power
standby mode.
EP
Exposed
Pad
Connect to Ground. The exposed pad must be soldered to the circuit board ground plane for proper
thermal and electrical performance.
IN+
IN-
EN
LIMITER
5Gbps EQUALIZER
OUT+
OUT-
VCC
EQUALIZER
OFFSET
CANCELLATION
LOWPASS FILTER
50
Ω
100
Ω
40k
Ω
50
Ω
VCC
MAX3784/
MAX3784A
Figure 2. Functional Diagram
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