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參數(shù)資料
| 型號： | MAX3775CEE |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Quad LVDS Receiver with Flow-Through Pinout 16-SOIC -40 to 85 |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO16 |
| 封裝： | 0.150 INCH, QSOP-16 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大小： | 220K |
| 代理商： | MAX3775CEE |
Loop Filter, VCO, and Latch
The phase detector and frequency detector outputs are
summed into a loop filter. An external capacitor
(between CF+ and CF-) is required to set the PLL
damping factor. The fully integrated VCO contains an
internal current reference and filter circuitry to minimize
the influence of V
CC
noise. The VCO creates a clock
output with frequency proportional to the control volt-
age applied by the loop filter. Data recovery is accom-
plished by using the recovered clock signal to latch the
incoming data to the CML output buffers, significantly
reducing output jitter.
LOCK Output
An active high LOCK output monitor derived from the
frequency detector indicates that the PLL is frequency-
locked onto the input data. Without input data, the
LOCK signal may settle high or low. The use of a low-
pass RC filter is recommended to reduce the effects of
chatter that could be caused by high input-jitter con-
tent. For optimum jitter performance, keep the load
≥
15k
on the output of the LOCK pin.
RATESEL Input
The RATESEL input is used to select between input
data rates of 2.125Gbps and 1.0625Gbps. This func-
tion allows the repeater to sample data at the correct
data rate by selecting a divide-by-2 network, giving
maximum jitter tolerance at both data rates. The loop
bandwidth of the repeater scales with the selected fre-
quency; i.e., the loop-bandwidth at an input rate of
1.0625Gbps is half that at the input rate of 2.125Gbps.
See the
Applications Information
section for the func-
tionality of the RATESEL pin.
Applications Information
Input and Output Terminations
Figures 3 and 4 show models for the MAX3772
–
MAX3775 inputs and outputs, including packaging parasitics.
M
Dual-Rate Fibre Channel Repeaters
_______________________________________________________________________________________
7
ESD
STRUCTURES
IN+
0.2pF
PACKAGE
1.5nH
1.5nH
0.4pF
0.4pF
V
CC
- 0.450V
0.2pF
OPTIONAL
50
OR 75
1k
V
CC
Figure 3. Input Structure
IN+
IN-
LOOP
FILTER
VCO
÷
2
1
0
OUT+
OUT-
V
CC
CLK+
CLK-
LOCK
V
CC
D
Q
RATESEL
CLKEN
CF+
CF-
0.047
μ
F
PHASE/FREQ
DETECTOR
OPTIONAL
50
OR 75
OPTIONAL
100
OR 150
TERMINATION
Figure 2. Block Diagram
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| MAX3781UCM-TD | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
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