參數(shù)資料
型號: MAX3774CEE
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 通信及網(wǎng)絡
英文描述: Process/Temperature Controller; Control Operation:Auto/Manual, Ramp/Soak, Stand By, Valve Positioning; Control Output Current:4-20 mA; Control Output Relay Rating:264 VAC / 2 A; Control Type:On/Off, PID RoHS Compliant: NA
中文描述: SPECIALTY TELECOM CIRCUIT, PDSO16
封裝: 0.150 INCH, QSOP-16
文件頁數(shù): 3/9頁
文件大?。?/td> 220K
代理商: MAX3774CEE
M
Dual-Rate Fibre Channel Repeaters
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, 8B/10B data coding, C
F
= 0.047μF, lock pin loaded with
15k
resistor, all high-speed inputs and outputs
AC-coupled, T
A
= 0
°
C to +70
°
C, unless otherwise noted. Typical values are at V
CC
= +3.3V, T
A
= +25
°
C.)
PARAMETER
CONDITIONS
MIN
78
118
78
118
TYP
100
150
100
150
100
40
10
MAX
122
182
122
182
UNITS
MAX3772/MAX3774
MAX3773/MAX3775
MAX3772/MAX3773
MAX3774/MAX3775
10Hz
f
<
100Hz
100Hz
f
<
1MHz
1MHz
f
<
2.5GHz
Differential Input Resistance
(IN )
Differential Output Resistance
(OUT , CLK )
Supply Noise Tolerance
(Note 4)
mVp-p
OPERATION AT 2.125Gbps
(Note 2)
Input = K28.7 (Note 5)
Input = CRPAT (Note 6)
Input = CRPAT (Notes 6, 7)
Input = K28.5 (Note 8)
Input = RPAT (Notes 7, 9)
Input = RPAT (Notes 7, 9, 10)
4.4
2.8
2.9
Random Jitter Generation at
OUT and CLK
ps
RMS
22
48
99
Deterministic Jitter on OUT
psp-p
Total Jitter at OUT
psp-p
f = 85kHz
f = 1270kHz
f = 10MHz
1.5
0.1
0.1
Sinusoidal Component of Jitter
Tolerance (BER = 10
-12
)
Input = CJTPAT
(Notes 3, 7)
UI
Total High-Frequency Jitter
Tolerance
Jitter Transfer Bandwidth
Jitter Transfer Peaking
Propagation Delay
Clock to Q Delay
OPERATION AT 1.0625Gbps
(Note 2)
Input = CJTPAT (Notes 3, 7, 9)
0.7
UI
Measured with 50% edge density
(Note 11)
11
0.05
1.5
300
MHz
dB
ns
ps
1.0
280
Falling clock to data transition
150
Input = K28.7 (Note 5)
Input = CRPAT (Note 6)
Input = CRPAT (Notes 6, 7)
Input = K28.5 (Note 8)
Input = RPAT (Notes 7, 9)
Input = RPAT (Notes 7, 9, 10)
6.2
3.6
4.9
Random Jitter Generation at
OUT and CLK
ps
RMS
40
75
160
Deterministic Jitter on OUT
psp-p
Total Jitter at OUT
psp-p
f = 42.5kHz
f = 635kHz
f = 5MHz
1.5
0.1
0.1
Sinusoidal Component of Jitter
Tolerance (BER = 10
-12
)
Input = CJTPAT
(Notes 3, 7)
UI
Total High-Frequency Jitter
Tolerance
Input = CJTPAT (Notes 3, 7, 9)
0.7
UI
Jitter Transfer Bandwidth
Jitter Transfer Peaking
Propagation Delay
Clock to Q Delay
Measured with 50% edge density
(Note 11)
6
MHz
dB
ns
ps
0.05
5
740
Falling clock to data transition
200
510
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