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參數資料
| 型號： | MAX3680EAI+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 4/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DESERIALZR 622MBPS TTL 28SSOP |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,000 |
| 功能： | 解串器 |
| 數據速率： | 622Mbps |
| 輸入類型： | PECL |
| 輸出類型： | TTL |
| 輸入數： | 1 |
| 輸出數： | 8 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應商設備封裝： | 28-SSOP |
| 包裝： | 帶卷 (TR) |
MAX3680/MAX3680A
Detailed Description
The MAX3680/MAX3680A deserializer uses an 8-bit
shift register, 8-bit parallel output register, 3-bit counter,
PECL input buffers, and TTL input/output buffers to
convert 622Mbps serial data to 8-bit-wide, 77Mbps par-
allel data (Figure 1).
The input shift register continuously clocks incoming
data on the positive transition of the serial clock (SCLK)
input signal. The 3-bit counter generates a parallel output
clock (PCLK) by dividing down the serial clock frequen-
cy. The PCLK signal is used to clock the parallel output
register. During normal operation, the counter divides the
SCLK frequency by eight, causing the output register to
latch every eight bits of incoming serial data.
The MAX3680 synchronization input (SYNC) is used for
data realignment and reframing. When the SYNC signal
is pulsed high for at least two SCLK cycles, PCLK is
delayed by one SCLK cycle, causing the first incoming
bit of the serial input data stream to be dropped. This
realignment is guaranteed to occur within two PCLK
cycles of the SYNC rising edge.
See Figure 2 for the functional timing diagrams and
Figure 3 for the timing parameters diagram.
+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs
4
_______________________________________________________________________________________
Pin Description
8-BIT
SHIFT
REGISTER
8-BIT
PARALLEL
OUTPUT
REGISTER
3-BIT
COUNTER
TTL
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PCLK
TTL
PECL
SYNC
MAX3680/
MAX3680A
SD+
SD-
SCLK+
SCLK-
Figure 1. Functional Diagram
PIN
MAX3680
MAX3680A
NAME
FUNCTION
1, 2, 5, 8,
14, 18, 25
1, 2, 5, 8,
14, 18, 25
VCC
+3.3V Supply Voltage
3
SD+
Noninverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive
transition.
4
SD-
Inverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive transition.
6
SCLK+
Noninverting PECL Serial Clock Input
7
SCLK-
Inverting PECL Serial Clock Input
9, 11, 12,
16, 20, 23,
27
11, 12, 16,
20, 23, 27
GND
Ground
10
—
SYNC
TTL Synchronization Pulse Input. Pulse high for at least two SCLK periods to shift the data
alignment by dropping one bit in the serial input data stream.
—
9, 10
N.C.
No Connection
13
PCLK
TTL Parallel Clock Output
15, 17, 19,
21, 22, 24,
26, 28
15, 17, 19,
21, 22, 24,
26, 28
PD0–PD7
TTL Parallel Data Outputs. Data is updated on the falling edge of PCLK. See Figure 2 for the
relationship between serial-data-bit position and output-data-bit assignment.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MAX3680EVKIT | 功能描述:界面開發(fā)工具 Evaluation Kit for the MAX3680 RoHS:否 制造商:Bourns 產品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| MAX3681EAG | 功能描述:串行器/解串器 - Serdes 3.3V 622Mbps SDH/ SONET 1:8 Deserializ RoHS:否 制造商:Texas Instruments 類型:Deserializer 數據速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數量:1 輸出端數量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX3681EAG+ | 功能描述:串行器/解串器 - Serdes 3.3V 622Mbps SDH/ SONET 1:8 Deserializ RoHS:否 制造商:Texas Instruments 類型:Deserializer 數據速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數量:1 輸出端數量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX3681EAG+T | 功能描述:串行器/解串器 - Serdes 3.3V 622Mbps SDH/ SONET 1:8 Deserializ RoHS:否 制造商:Texas Instruments 類型:Deserializer 數據速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數量:1 輸出端數量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX3681EAG-T | 功能描述:串行器/解串器 - Serdes 3.3V 622Mbps SDH/ SONET 1:8 Deserializ RoHS:否 制造商:Texas Instruments 類型:Deserializer 數據速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數量:1 輸出端數量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
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