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參數(shù)資料
| 型號(hào)： | MAX3680 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | DIODE SWITCHING SINGLE 75V 125mA-Io 150mW 4ns-trr SOD-523 3K/REEL |
| 中文描述： | +3.3V、622Mbps、SDH/SONET 1:8解串器，TTL輸出 |
| 文件頁(yè)數(shù)： | 4/8頁(yè) |
| 文件大?。?/td> | 78K |
| 代理商： | MAX3680 |
M
_______________Detailed Desc ription
The MAX3680 deserializer uses an 8-bit shift register,
8-bit parallel output register, 3-bit counter, PECL input
buffers, and TTL input/output buffers to convert
622Mbps serial data to 8-bit-wide, 77Mbps parallel
data (Figure 1).
The input shift register continuously clocks incoming
data on the positive transition of the serial clock (SCLK)
input signal. The 3-bit counter generates a parallel out-
put clock (PCLK) by dividing down the serial clock fre-
quency. The PCLK signal is used to clock the parallel
output register. During normal operation, the counter
divides the SCLK frequency by eight, causing the out-
put register to latch every eight bits of incoming serial
data.
The synchronization input (SYNC) is used for data
realignment and reframing. When the SYNC signal is
pulsed high for at least two SCLK cycles, PCLK is
delayed by one SCLK cycle, causing the first incoming
bit of the serial input data stream to be dropped. This
realignment is guaranteed to occur within two PCLK
cycles of the SYNC rising edge.
See Figure 2 for the functional timing diagrams and
Figure 3 for the timing parameters diagram.
+3.3V, 622Mbps, S DH/S ONET
1:8 Deserializer with T T L Outputs
4
_______________________________________________________________________________________
______________________________________________________________Pin Desc ription
NAME
FUNCTION
1, 2, 5, 8,
14, 18, 25
V
CC
+3.3V Supply Voltage
3
SD+
Noninverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive transition.
PIN
4
SD-
Inverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive transition.
6
SCLK+
Noninverting PECL Serial Clock Input
10
SYNC
TTL Synchronization Pulse Input. Pulse high for at least two SCLK periods to shift the data align-
ment by dropping one bit in the serial input data stream.
9, 11, 12, 16,
20, 23, 27
GND
Ground
7
SCLK-
Inverting PECL Serial Clock Input
15, 17, 19, 21,
22, 24, 26, 28
PD0–PD7
TTL Parallel Data Outputs. Data is updated on the falling edge of PCLK. See Figure 2 for the relation-
ship between serial-data-bit position and output-data-bit assignment.
13
PCLK
TTL Parallel Clock Output
8-BIT
SHIFT
REGISTER
8-BIT
PARALLEL
OUTPUT
REGISTER
3-BIT
COUNTER
TTL
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PCLK
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
PECL
PECL
SYNC
MAX3680
SD+
SD-
SCLK+
SCLK-
Figure 1. Functional Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX3680AEAI | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| MAX3680EAI | 功能描述:串行器/解串器 - Serdes 3.3V 622Mbps SDH/ SONET 1:8 Deserializ RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX3680EAI+ | 功能描述:串行器/解串器 - Serdes 3.3V 622Mbps SDH/ SONET 1:8 Deserializ RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX3680EAI+T | 功能描述:串行器/解串器 - Serdes 3.3V 622Mbps SDH/ SONET 1:8 Deserializ RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX3680EAI-T | 功能描述:串行器/解串器 - Serdes 3.3V 622Mbps SDH/ SONET 1:8 Deserializ RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
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