參數(shù)資料
型號(hào): MAX3665EUA
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 數(shù)字傳輸電路
英文描述: 622Mbps, Ultra-Low-Power, 3.3V Transimpedance Preamplifier for SDH/SONET
中文描述: ATM/SONET/SDH SUPPORT CIRCUIT, PDSO8
封裝: MO-187C-AA, MICRO MAX PACKAGE-8
文件頁數(shù): 7/12頁
文件大?。?/td> 584K
代理商: MAX3665EUA
If the amount of tolerable noise is known, then the filter
capacitor can be easily selected:
(
(
FILT
For example, with maximum noise voltage = 100mVp-p,
C
PHOTO
= 0.5pF, R
FILT
= 1.5k
, and I
NOISE
selected
to be 6nA (1/10 of MAX3665 input-referred noise):
)
(
Figure 4 shows the suggested layout for a TO-46 header
Step 3: Designing a Low-Capacitance Input
Noise performance and bandwidth are adversely
affected by stray capacitance on the input node. Select
a low-capacitance photodiode and use good high-fre-
quency design and layout techniques to minimize
capacitance on this pin. The MAX3665 is optimized for
0.5pF of capacitance on the input—approximately the
capacitance of a photodetector diode sharing a com-
mon header with the MAX3665 in die form.
Photodiode capacitance changes significantly with bias
voltage. With a +3.3V supply voltage, the reverse voltage
on the PIN diode is only 2.5V. If a higher voltage supply
is available, apply it to the diode to significantly reduce
capacitance.
Take great care to reduce input capacitance. With the
μMAX version of the MAX3665, the package capaci-
tance is about 0.3pF, and the PC board between the
MAX3665 input and the photodiode can add parasitic
capacitance. Keep the input line short, and remove
power and ground planes beneath it. Packaging the
MAX3665 into a header with the photodiode provides
the best possible performance. It reduces parasitic
capacitance to a minimum, resulting in the lowest noise
and the best bandwidth.
Wire Bonding
For high current density and reliable operation, the
MAX3665 uses gold metallization. Make connections to
the die with gold wire only, and use ball-bonding tech-
niques (wedge-bonding is not recommended). Die-pad
size is 4 mils square. Die thickness is 12 mils.
V
CC
and Ground
Use good high-frequency design and layout tech-
niques. The use of a multilayer circuit board with sepa-
rate ground and V
CC
planes is recommended. Take
care to bypass V
CC
and to connect the GND pin to the
ground plane with the shortest possible traces.
C
= 0.1
FILT
)
(
(
)
0 5 10
.
1500 6 10
5 6
12
4
/
. nF
M
622Mbps, Ultra-Low-Power, 3.3V
Transimpedance Preamplifier for SDH/SONET
_______________________________________________________________________________________
7
C
=
V
FILT
NOISE
R
)(
)(
)
)
C
I
PHOTO
NOISE
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