For example, with maximum noise voltage " />
參數(shù)資料
型號: MAX3665EUA+T
廠商: Maxim Integrated Products
文件頁數(shù): 8/10頁
文件大?。?/td> 0K
描述: IC PREAMP 622MBPS TRANS 8-UMAX
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: 轉(zhuǎn)阻前置放大器
應(yīng)用: 光纖學(xué)網(wǎng)絡(luò)
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-uMAX
包裝: 帶卷 (TR)
If the amount of tolerable noise is known, then the filter
capacitor can be easily selected:
For example, with maximum noise voltage = 100mVP-P,
CPHOTO = 0.5pF, RFILT = 1.5k
, and INOISE selected
to be 6nA (1/10 of MAX3665 input-referred noise):
Figure 4 shows the suggested layout for a TO-46 header
Step 3: Designing a Low-Capacitance Input
Noise performance and bandwidth are adversely
affected by stray capacitance on the input node. Select
a low-capacitance photodiode and use good high-fre-
quency design and layout techniques to minimize
capacitance on this pin. The MAX3665 is optimized for
0.5pF of capacitance on the input—approximately the
capacitance of a photodetector diode sharing a com-
mon header with the MAX3665 in die form.
Photodiode capacitance changes significantly with bias
voltage. With a +3.3V supply voltage, the reverse voltage
on the PIN diode is only 2.5V. If a higher voltage supply
is available, apply it to the diode to significantly reduce
capacitance.
Take great care to reduce input capacitance. With the
MAX version of the MAX3665, the package capaci-
tance is about 0.3pF, and the PC board between the
MAX3665 input and the photodiode can add parasitic
capacitance. Keep the input line short, and remove
power and ground planes beneath it. Packaging the
MAX3665 into a header with the photodiode provides
the best possible performance. It reduces parasitic
capacitance to a minimum, resulting in the lowest noise
and the best bandwidth.
Wire Bonding
For high current density and reliable operation, the
MAX3665 uses gold metallization. Make connections to
the die with gold wire only, and use ball-bonding tech-
niques (wedge-bonding is not recommended). Die-pad
size is 4 mils square. Die thickness is 16 mils.
VCC and Ground
Use good high-frequency design and layout tech-
niques. The use of a multilayer circuit board with sepa-
rate ground and VCC planes is recommended. Take
care to bypass VCC and to connect the GND pin to the
ground plane with the shortest possible traces.
C
= 0.1
FILT
()
() ()()
=
05 10
1500 6 10
5 6
12
4
.
/
. nF
C
=
V
FILT
NOISE
()(
)
()(
)
C
RI
PHOTO
FILT
NOISE
MAX3665
622Mbps, Ultra-Low-Power, 3.3V
Transimpedance Preamplifier for SDH/SONET
_______________________________________________________________________________________
7
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