
M
wavelength:
λ
= 1.3μm, threshold current: I
TH
= 22mA
at +25
°
C, threshold temperature coefficient:
β
TH
=
1.3%/
°
C, laser-to-monitor transfer:
ρ
MON
= 0.2A/W
(
ρ
MON
=
ρ
MONITORDIODE
x L
LASER-TO-MONITORDIODE)
,
and laser slope efficiency:
η
= 0.05mW/mA at +25
°
C.
Determining R
APCSET
The desired monitor diode current is estimated by I
MD
=
P
AVG
ρ
MON
= 200μA. The I
MD
vs. R
APCSET
graph in the
Typical Operating Characteristics
shows R
APCSET
at 12k
.
Determining R
MODSET
Assuming r
e
= 10 and an average power of 0dBm (1mW),
the peak-to-peak optical power P
P-P
= 1.64mW (Table 1).
The required modulation current is 1.64(mW)/0.05(mW/mA)
= 32.8mA. The I
MOD
vs. R
MODSET
graph in the
Typical
Operating Characteristics
shows R
MODSET
at 9k
.
Determining R
BIASMAX
Determine the maximum threshold current (I
TH(MAX)
) at
T
A
= +85
°
C and end of life. Assuming (I
TH(MAX)
) =
50mA, the maximum bias current should be:
I
BIASMAX
= I
TH(MAX)
In this example, I
BIASMAX
= 50mA. The I
BIASMAX
vs. R
BIASMAX
graph in the
Typical Operating Charact-
eristics
shows R
BIASMAX
at 8k
.
Wire-Bonding Die
For high-current density and reliable operation, the
MAX3656 uses gold metalization. Make connections to
the die with gold wire only, using ball-bonding tech-
niques. Die-pad size is 4.03 mils (102.4μm) square,
and die size is 98 mils
65 mils (2489.2μm
1651μm).
Layout Considerations
To minimize inductance, keep the connections between
the MAX3656 output pins and laser diode as close as
possible. Optimize the laser diode performance by
placing a bypass capacitor as close as possible to the
laser anode. Take extra care to minimize stray parasitic
capacitance on the BIAS and MD pins. Use good high-
frequency layout techniques and multilayer boards with
uninterrupted ground planes to minimize EMI and
crosstalk.
155Mbps to 2.5Gbps Burst-Mode
Laser Driver
12
______________________________________________________________________________________
Table 3. Pad Locations
PAD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
NAME
V
CC
IN+
IN-
V
CC
BEN+
BEN-
GND
EN
GND
V
CC
FAIL
GND
LONGB
GND
BIAS-
BIAS+
V
CC
OUT+
OUT+
OUT-
OUT-
V
CC
GND
MD
GND
V
CC
GND
BIASMAX
MODSET
APCSET
GND
COORDINATES (microns)
51.2
51.2
51.2
51.2
51.2
51.2
142.2
282.2
423.6
608.4
1569.6
1738.2
1881.0
2023.8
2257.6
2257.6
2257.6
2257.6
2257.6
2257.6
2257.6
2257.6
2039.2
1893.6
1749.4
1603.8
1461.0
700.8
555.2
412.4
262.6
1146.0
1003.2
856.2
709.2
198.2
51.2
-111.2
-111.2
-111.2
-111.2
-111.2
-111.2
-111.2
-111.2
87.6
236.0
453.0
626.6
768.0
931.8
1073.2
1217.4
1242.6
1242.6
1242.6
1242.6
1242.6
1242.6
1242.6
1242.6
1242.6
Figure 7. Single-Ended LVTTL or LVCMOS Biasing for Burst
Enable
IN+
IN-
BEN+
BEN-
LVTTL OR LVCMOS HIGH
LVTTL OR LVCMOS LOW
V
CC
R
5
= 1k
R
4
= 4k
R
6
= 9k
V
CC
R
3
= 1k
MAX3656