
M
3.3V, 622Mbps LVDS,
Dual 4:2 Crosspoint Switch
8
_______________________________________________________________________________________
Figure 4. LVDS Input Model
MAX3640
DIA1+
50
50
1.5k
1.5k
DIA1-
V
CC
V
CC
5k
25k
V
CC
Applications Information
Interfacing LVPECL Outputs to
MAX3640 LVDS Inputs
To DC-couple between LVPECL and LVDS, use the
resistor network shown in Figure 3. Note that the
LVPECL output is optimized for a 50
load to V
CC
- 2V,
so an equivalent network is used. Also, the network
attenuation should be such that the LVPECL output sig-
nal after attenuation is well within the LVDS input range.
Note that the LVDS input impedance is a true 100
between the inputs. The differential impedance does
not contribute to the DC termination impedance, but
does contribute to the AC termination impedance. This
means that AC and DC impedance will always be dif-
ferent.
Layout Techniques
For best performance, use good high-frequency layout
techniques. Filter voltage supplies, and keep ground
connections short. Use multiple vias where possible.
Also, use controlled-impedance transmission lines to
interface with the MAX3640 data inputs and outputs.
Interface Models
Figure 4 shows the interface model for the LVDS
inputs, while Figure 5 shows the model for the LVDS
outputs.