參數(shù)資料
型號(hào): MAX3395EEBC+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 20/20頁(yè)
文件大?。?/td> 0K
描述: IC LVL XLTR LV 6MBPS 12-UCSP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
邏輯功能: 變換器,雙向,3 態(tài)
位數(shù): 4
輸入類型: 邏輯
輸出類型: 邏輯
數(shù)據(jù)速率: 6Mbps
通道數(shù): 4
輸出/通道數(shù)目: 1
差分 - 輸入:輸出: 無(wú)/無(wú)
傳輸延遲(最大): 50ns
電源電壓: 1.65 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 12-WFBGA,WLCSP
供應(yīng)商設(shè)備封裝: 12-UCSP(3x4)
包裝: 帶卷 (TR)
capacitive isolation between I/O lines. When one or
both I/O lines are at a logic-low level, the gate-control
logic turns the pass-FET on. When the pass-FET is
active, I/O VL_ and I/O VCC_ are connected, allowing
the logic-low signal to be expressed simultaneously on
both I/O lines.
The MAX3394E/MAX3395E/MAX3396E have internal
10k
Ω (typ) pullup resistors from I/O VL_ and I/O VCC_
to the respective supply voltages, allowing operation
with open-drain drivers. Internal slew-rate enhancement
circuitry accelerates logic-state transitions, maintaining
a fast data rate with a higher bus load capacitance.
Additionally, the 10mA current sink drivers permit the
use of smaller external pullup resistors.
Internal Slew-Rate Enhancement
Internal slew-rate enhancement circuitry accelerates
logic-state changes by turning on MOSFETs MP1 and
MP2 during low-to-high logic transitions, and MOSFETs
MN3 and MN4 during high-to-low logic transitions (see
the
Functional Diagram). During logic-state changes,
speed-up MOSFETS are triggered by I/O line voltage
thresholds. MOSFETS MN3 and MN4 sink 10mA during
high-to-low logic transitions. MP1 and MP2 source 15mA
during low-to-high logic transitions. Slew-rate enhance-
ment allows a fast data rate despite large capacitive bus
loads, and permits larger external pullup resistors.
MAX3394E/MAX3395E/MAX3396E
±15kV ESD-Protected, High-Drive Current, Dual-/Quad-/
Octal-Level Translators with Speed-Up Circuitry
_______________________________________________________________________________________
9
MAX3394E
MAX3395E
MAX3396E
tFVL
tRVL
tI/OVCC-VL
I/O VL_
I/O VCC_
VL
VCC
10%
90%
50%
VCC
CIOVL
tI/OVCC-VL
I/O VCC
VL
VCC
EN
50
Ω
I/O VL
Figure 3. Push-Pull Driving I/O VCC_ Test Circuit and Timing
MAX3394E
MAX3395E
MAX3396E
tI/OVCC-VL
I/O VL_
I/O VCC_
VL
VCC
10%
90%
50%
VCC
CIOVL
tI/OVCC-VL
I/O VL
VL
VCC
EN
tFVL
tRVL
VGATE
Figure 4. Open-Drain Driving I/O VCC_ Test Circuit and Timing
相關(guān)PDF資料
PDF描述
D38999/26MJ4SD CONN PLUG 56POS STRAIGHT W/SCKT
MAX3378EEBC+T IC LVL XLTR LV 8MBPS 12UCSP
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