參數(shù)資料
型號: MAX3394EETA+T
廠商: Maxim Integrated Products
文件頁數(shù): 15/20頁
文件大?。?/td> 0K
描述: IC LVL XLTR LV 6MBPS 8TDFN
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1
邏輯功能: 變換器,雙向,3 態(tài)
位數(shù): 2
輸入類型: 邏輯
輸出類型: 邏輯
數(shù)據(jù)速率: 6Mbps
通道數(shù): 2
輸出/通道數(shù)目: 1
差分 - 輸入:輸出: 無/無
傳輸延遲(最大): 50ns
電源電壓: 1.65 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-WFDFN 裸露焊盤
供應商設備封裝: 8-TDFN-EP(3x3)
包裝: 標準包裝
其它名稱: MAX3394EETA+TDKR
MAX3394E/MAX3395E/MAX3396E
±15kV ESD-Protected, High-Drive Current, Dual-/Quad-/
Octal-Level Translators with Speed-Up Circuitry
4
_______________________________________________________________________________________
TIMING CHARACTERISTICS
(VCC = +1.65V to +5.5V, VL = +1.2V to VCC; CIOVL
≤ 15pF, CIOVCC ≤ 15pF; TA = -40°C to +85°C, unless otherwise noted. Typical val-
ues are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Push-pull driver, Figure 1
50
I/O VCC_ Rise Time
tRVCC
Open-drain driver, internal pullup, Figure 2
500
ns
Push-pull driver, Figure 1
50
I/O VCC_ Fall Time
tFVCC
Open-drain driver, internal pullup, Figure 2
50
ns
Push-pull driver, Figure 3
50
I/O VL_ Rise Time
tRVL
Open-drain driver, internal pullup, Figure 4
500
ns
Push-pull driver, Figure 3
50
I/O VL_ Fall Time
tFVL
Open-drain driver, internal pullup, Figure 4
50
ns
Push-pull driver, Figure 1
50
tI/OVL-VCC
Open-drain driver, internal pullup, Figure 2
600
Push-pull driver, Figure 3
50
Propagation Delay
tI/OVCC-VL
Open-drain driver, internal pullup, Figure 4
600
ns
Propagation Delay After EN
tEN
Push-pull or open-drain driver, Figure 5
5
s
Push-pull driver
5
Channel-to-Channel Skew
tSKEW
Open-drain driver, internal pullup
100
ns
Push-pull driver, Figures 1, 3
6
Maximum Data Rate
Open-drain driver, internal pullup,
Figures 2, 4
1
Mbps
Note 1: All units are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design
and not production tested.
Note 2: During a low-to-high transition, the threshold at which the I/O changes state is the lower of VILL and VILC since the two sides
are internally connected by an internal switch while the device is in the logic-low state.
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