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參數(shù)資料
| 型號： | MAX335MRG |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | Serial Controlled, 8-Channel SPST Switch |
| 中文描述： | OCTAL 1-CHANNEL, SGL POLE SGL THROW SWITCH, CDIP24 |
| 封裝： | CERAMIC, DIP-24 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大小： | 121K |
| 代理商： | MAX335MRG |
M
S erial Controlled, 8-Channel S PS T S witc h
4
_______________________________________________________________________________________
PARAMETER
DOUT Data-Hold Time After Rising
SCLK (Note 4)
SYMBOL
f
SCLK
t
CH +
t
CL
t
CSS
MIN
2.1
480
240
TYP
MAX
0
UNITS
MHz
ns
ns
Data-Setup Time
Data-Hold Time
t
DS
t
DH
ns
200
0
Rise Time of DOUT (Note 3)
ns
ns
SCLK Low Time
100
t
CL
190
ns
SCLK High Time
t
CH
190
ns
ns
CS
Lag Time
t
CSH2
240
ns
DOUT Data Valid After
Falling SCLK
t
DO
240
2
ns
μs
Fall Time of DOUT (Note 3)
100
ns
Cycle Time
CS
Lead Time
SCLK Maximum Frequency
2
μs
CONDITIONS
C
L
= 10pF
20% V
L
to 70% V
L
, C
L
= 10pF
20% V
L
to 70% V
L
, C
L
= 10pF
70% V
L
to 20% V
L
, C
L
= 10pF
70% V
L
to 20% V
L
, C
L
= 10pF
Note 4:
This specification guarantees that data at D
OUT
never appears before SCLK's falling edge.
TIMING CHARACTERISTICS OF SERIAL DIGITAL INTERFACE
(Figure 1)
(V
L
= +5V ±10%, V+ = +15V, V- = -15V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
400
T
A
= +25°C
Allowable Fall Time at DIN,
SCLK,
CS
(Note 3)
Allowable Rise Time at DIN,
SCLK,
CS
(Note 3)
50% of SCLK to 10% of
DOUT CL = 10pF
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