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參數(shù)資料
| 型號(hào)： | MAX3346EEUD+T |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 4/17頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC USB TXRX ESD PROTECT 14TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類(lèi)型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 1/1 |
| 規(guī)程： | USB 2.0 |
| 電源電壓： | 4 V ~ 5.5 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 帶卷 (TR) |
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MAX3346E
±15kV ESD-Protected USB Transceiver
in UCSP
12
______________________________________________________________________________________
External Components
External Resistors
Two external resistors are required for USB connection,
each of them from 23.7 ±1% to 27.4 ±1%, 1/2W (or
greater). Place one resistor in series between D+ of the
MAX3346E and D+ of the USB connector. Place the
other resistor in series between D- of the MAX3346E
and D- of the USB connector. The Typical Operating
Circuit shows these connections.
External Capacitors
Four external capacitors are recommended for proper
operation. Use a 0.1F ceramic for decoupling VL, a
1F ceramic capacitor for decoupling VCC, and a 1.0F
(or greater) ceramic or plastic filter capacitor on VTRM.
Return all capacitors to GND.
Receiving Data from the USB
Data received from the USB are output to VP/VM and
RCV in either of two ways, differentially or single ended.
To receive data from the USB, force OE high, and force
SUSP low. Differential data arriving at D+/D- appears
as differential logic signals at VP/VM, and as a single-
ended logic signal at RCV. If both D+ and D- are low,
then VP and VM are low, signaling an SE0 condition on
the bus; RCV retains the last state before SE0 (see
Table 3).
Transmitting Data to the USB
The MAX3346E outputs data to the USB differentially on
D+ and D-. The logic driving the signals may be either
differential or single ended. For sending differential
logic, force MODE high, force OE and SUSP low, and
apply data to VP and VM. If sending single-ended
logic, force MODE, SUSP, OE, and VM low, and apply
data to VP. With VP low, D+ is low and D- high, result-
ing in a logic 0 state. With VP high, D+ is high and D-
low, resulting in a logic 1 state (see Table 3).
ESD protection
To protect the MAX3346E against ESD, D+ and D- have
extra protection against static electricity to protect the
device up to ±15kV. The ESD structures withstand high
ESD in all states; normal operation, suspend, and pow-
ered down. For the 15kV ESD structures to work cor-
rectly, a 1F or greater capacitor must be connected
from VTRM to GND.
ESD protection can be tested in various ways; the D+
and D- input/output pins are characterized for protection
to the following limits:
1) ±15kV using the Human Body Model.
2) ±8kV using the Contact Discharge method specified
in IEC 1000-4-2.
3) ±10kV using the IEC 1000-4-2 Air-Gap method.
ESD Test Conditions
ESD performance depends on a variety of conditions.
Contact Maxim for a reliability report that documents
test setup, test methodology, and test results.
Human Body Model
Figure 6a shows the Human Body Model, and Figure 6b
shows the current waveform it generates when dis-
charged into a low impedance. This model consists of a
100pF capacitor charged to the ESD voltage of interest,
which is then discharged into the test device through a
1.5k resistor.
CHARGE-CURRENT
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
100pF
RC
1M
RD
1500
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
Figure 6a. Human Body ESD Test Models
IP 100%
90%
36.8%
tRL
TIME
tDL
CURRENT WAVEFORM
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
Ir
10%
0
AMPERES
Figure 6b. Human Body Model Current Waveform
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