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參數(shù)資料
| 型號： | MAX3295AUT-T |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 20Mbps, +3.3V, SOT23 RS-485/ RS-422 Transmitters |
| 中文描述： | LINE DRIVER, PDSO6 |
| 封裝： | MO-178, SOT-23, 6 PIN |
| 文件頁數(shù)： | 9/11頁 |
| 文件大小： | 316K |
| 代理商： | MAX3295AUT-T |
M
20Mbps, +3.3V, SOT23 RS-485/
RS-422 Transmitters
_______________________________________________________________________________________
9
Hot-Swap Input Circuitry
The MAX3293/MAX3294/MAX3295 enable input fea-
tures hot-swap capability. At the input, there are two
NMOS devices, M1 and M2 (Figure 6). When V
CC
ramps from zero, an internal 10μs timer turns on M2
and sets the SR latch, which also turns on M1.
Transistors M2, a 2mA current sink, and M1, a 100μA
current sink, pull DE to GND through a 5.6k
resistor.
M2 is designed to pull DE to the disabled state against
an external parasitic capacitance up to 100pF that may
drive DE high. After 10μs, the timer deactivates M2
while M1 remains on, holding DE low against three-
state leakages that can drive DE high. M1 remains on
until an external source overcomes the required input
current. At this time, the SR latch resets and M1 turns
off. When M1 turns off, DE reverts to a standard, high-
impedance CMOS input. Whenever V
CC
drops below
1V, the hot-swap input is reset.
Hot-Swap Line Transient
During a hot-swap event when the driver is connected to
the line and is powered up, the driver must not cause the
differential signal to drop below 200mV. Figures 7, 8, and
9 show the results of the MAX3295 during power-up for
three different V
CC
ramp rates (0.1V/μs, 1V/μs, and
10V/μs). The photos show the V
CC
ramp, the single-
ended signal on each side of the 100
termination, as
well as the differential signal across the termination.
ESD Protection
Human Body Model
Figure 10 shows the Human Body Model, and Figure 11
shows the current waveform it generates when dis-
charged into low impedance. This model consists of a
100pF capacitor charged to the ESD voltage of interest,
which is then discharged into the device through a
1.5k
resistor.
Figure 8. Differential Power-Up Glitch (1V/μs)
Figure 9. Differential Power-Up Glitch (10V/μs)
Figure 11. Current Waveform
DIFFERENTIAL POWER-UP GLITCH
(10V/
μ
s)
200ns/div
2V/div
V
CC
Y
Z
Y-Z
0V
50mV/div
AC-COUPLED
50mV/div
AC-COUPLED
100mV/div
DIFFERENTIAL POWER-UP GLITCH
(1V/
μ
s)
1
μ
s/div
2V/div
V
CC
Y
Z
Y-Z
0V
100mV/div
AC-COUPLED
100mV/div
AC-COUPLED
200mV/div
Figure 10. Human Body ESD Test
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
100pF
R
C
1M
R
D
1.5k
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
I
P
100%
90%
36.8%
t
RL
TIME
t
DL
CURRENT WAVEFORM
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
Ir
10%
0V
0V
AMPERES
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