參數(shù)資料
型號: MAX3272EGP
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 數(shù)字傳輸電路
英文描述: +3.3V, 2.5Gbps Low-Power Limiting Amplifier
中文描述: ATM/SONET/SDH SUPPORT CIRCUIT, QCC20
封裝: 4 X 4 MM, 0.90 MM HEIGHT, MO-220, QFN-20
文件頁數(shù): 3/14頁
文件大?。?/td> 625K
代理商: MAX3272EGP
M
+3.3V, 2.5Gbps Low-Power
Limiting Amplifiers
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C. Typical values are at V
CC
= +3.3V and T
A
= +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
73
MAX
124.7
UNITS
mV
P-P
V
V
μA
High LOS Deassert Level
LOS Output High Voltage
LOS Output Low Voltage
Squelch Input Current
R
TH
= 80
(Notes 3, 10)
Sinking 30μA
Sourcing 1.2mA
2.4
0.4
400
Note 1:
Note 2:
Dice are designed and guaranteed from -40°C to +85°C but are tested only at T
A
= +25°C.
Supply current measurement excludes the current of the CML output stage (16mA typical). See Figure 1,
Power-Supply
Current Measurement
.
Guaranteed by design and characterization.
Input edge speed is controlled using 4-pole, lowpass Bessel filters with bandwidth approximately 75% of the maximum
data rate.
Deterministic jitter is measured with a K28.5 pattern (0011 1110 1011 0000 0101). Deterministic jitter is the peak-to-peak
deviation from ideal time crossings, measured at the zero-level crossings of the differential output per ANSI X3.230, Annex A.
Random jitter is measured with the minimum input signal. For Fibre Channel and Gigabit Ethernet applications, the peak-
to-peak random jitter is 14.1 times the RMS random jitter.
Power-supply noise rejection (PSNR) is calculated by the equation PSNR = 20log (
V
CC
/(
V
OUT
)), where
V
OUT
is the
change in differential output voltage due to the power-supply noise,
V
CC
. See Power-Supply Noise Rejection vs.
Frequency in the
Typical Operating Characteristics
.
Hysteresis is defined as: 20
log(V
LOS-DEASSERT
/V
LOS-ASSERT
).
Response time to a 10dB change in input power. For the specification guaranteed, the power is assumed to switch back
and forth between two levels (separated by 10dB and equidistant from assert and deassert levels) outside of the two
hysteresis thresholds.
Note 10:
All power-detect AC parameters are guaranteed with a 2
23
- 1 PRBS, 2.5Gbps input, with the longest possible run of 80CID.
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Typical Operating Characteristics
(V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted.)
600
650
700
750
800
850
900
950
1000
0
10
20
V
IN
(mV
P-P
)
30
40
50
OUTPUT AMPLITUDE
vs. INPUT AMPLITUDE
M
V
O
P
)
LEVEL = GND
LEVEL = OPEN
20
35
30
25
40
45
50
55
60
65
70
-40
10
-15
AMBIENT TEMPERATURE (
°
C)
35
60
85
SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
M
S
0
6
4
2
8
10
12
14
16
18
20
1
10
INPUT AMPLITUDE (mV
P-P
)
100
1000
10,000
DETERMINISTIC JITTER
vs. INPUT AMPLITUDE
M
D
P
)
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