參數(shù)資料
型號(hào): MAX3272AETP+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 13/14頁(yè)
文件大?。?/td> 0K
描述: IC AMP LIMITING 20-TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 75
類型: 限幅放大器
應(yīng)用: 光纖學(xué)網(wǎng)絡(luò)
安裝類型: 表面貼裝
封裝/外殼: 20-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 20-TQFN-EP(4x4)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 1387 (CN2011-ZH PDF)
CML Output Buffer
The MAX3272/MAX3272A CML output circuit (Figure 5)
provides high tolerance to impedance mismatches and
inductive connectors. The output current can be set to
two levels using the LEVEL pin. When LEVEL is uncon-
nected, the output current is approximately 16mA.
Connecting LEVEL to ground sets the output current to
approximately 20mA. The squelch function is enabled
when the SQUELCH pin is set to a TTL high. This func-
tion holds OUT+ and OUT- to a static level whenever
the input signal amplitude drops below the loss-of-sig-
nal threshold. This circuit is also equipped with a polari-
ty selector, programmed by the OUTPOL pin. When
this pin is connected to VCC, no inversion will occur.
When connected to ground, the output signal will be
inverted.
Design Procedure
Program the LOS Assert Threshold
External resistor RTH programs the loss-of-signal
threshold. See the LOS Threshold vs. RTH graph in the
the Typical Operating Characteristics section to select
the appropriate resistor.
Select the Coupling Capacitors
When AC-coupling, input and output coupling capaci-
tors (CIN and COUT) should be selected to minimize the
receiver’s deterministic jitter. Jitter is decreased as the
input low-frequency cutoff (fIN) is decreased:
fIN = 1 / [2
π(50)(CIN)]
For ATM/SONET or other applications using scrambled
NRZ data, select (CIN, COUT)
≥ 0.1F, which provides
fIN < 32kHz. For Fibre Channel, Gigabit Ethernet, or
other applications using 8B/10B data coding, select
(CIN, COUT)
≥ 0.01F, which provides fIN < 320kHz.
Refer to application note HFAN-1.1: Choosing AC-
Coupling Capacitors.
Select the Offset-Correction
Capacitor
The capacitor between CAZ1 and CAZ2 determines the
time constant of the signal path DC offset-cancellation
loop. To maintain stability, it is important to keep a one-
decade separation between fIN and the low-frequency
cutoff (fOC) associated with the DC offset-cancellation
circuit. For ATM/SONET or other applications using
scrambled NRZ data, fIN < 32kHz, so fOCMAX <
3.2kHz. Therefore, CAZ = 0.1F (fOC = 2kHz). For Fibre
Channel or Gigabit Ethernet applications, leave pins
CAZ1 and CAZ2 open.
Program the LOS Time Constant
External capacitor CCLOS programs the LOS assert
and deassert times. When inputting data with many
consecutive identical digits (CIDs), a longer time con-
stant may be advantageous, so LOS does not flag
incorrectly. In this case, connect the CLOS pin to a
0.01F capacitor to set the assert time in the range of
2s to 100s. For scrambled data where the mark den-
sity is kept at 50%, a shorter time constant may be
desirable. Leave the CLOS pin open for a shorter time
constant of about 1s.
MAX3272/MAX3272A
+3.3V, 2.5Gbps Low-Power
Limiting Amplifiers
8
_______________________________________________________________________________________
GND
LEVEL
ESD
STRUCTURES
VCC
50
50
OUT-
OUT+
Figure 5. CML Output Circuit
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MAX3272EGP 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述:
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