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參數(shù)資料
| 型號： | MAX3209EEUU+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 0K |
| 描述： | IC RS-232 DUAL SRL 38TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 6/10 |
| 規(guī)程： | RS232 |
| 電源電壓： | 10.8 V ~ 13.2 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 38-TFSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 38-TSSOP |
| 包裝： | 帶卷 (TR) |
MAX3209E
±15kV ESD-Protected, 12V, Dual RS-232 Serial Port
with Low-Power Standby for Motherboards/Desktops
6
_______________________________________________________________________________________
inputs and outputs) require this protection during man-
ufacturing. Therefore, the Machine Model is less rele-
vant to the I/O ports than are the Human Body Model
and IEC 1000-4-2.
±4kV Electrical Fast Transient/Burst Testing
(IEC 1000-4-4)
IEC 1000-4-4 Electrical Fast Transient/Burst (EFT/B) is
an immunity test for the evaluation of electrical and
electronic systems during operating conditions. The
test was adapted for evaluation of integrated circuits
with power applied. Repetitive fast transients with
severe pulsed EMI were applied to signal and control
ports. Over 15,000 distinct discharges per minute are
sent to each interface port of the IC or equipment under
test (EUT) simultaneously with a minimum test duration
time of one minute. This simulates stress due to dis-
placement current from electrical transients on AC
mains, or other telecommunication lines in close prox-
imity. Short rise times and very specific repetition rates
are essential to the validity of the test.
Stress placed on the EUT is severe. In addition to the
controlled individual discharges placed on the EUT,
extraneous noise and ringing on the transmission line
can multiply the number of discharges as well as
increase the magnitude of each discharge. All cabling
was left unterminated to simulate worst case reflections.
The MAX3209E was set up as specified in IEC 1000-4-4
and the Typical Operating Circuit of this data sheet.
The amplitude, pulse rise time, pulse duration, pulse
repetition period, burst duration, and burst period
(Figure 5) of the burst generator were all verified with a
tF2
tF1
tPHL
tPLH
tR1
tR2
1.5V
3.0V
0
DRIVER
INPUT
VOUT
VOH
VOL
3.3V
3.0V
-3.0V
-3.3V
RL
CL
SIGNAL
GENERATOR
Figure 1. Slew-Rate Test Circuit and Timing Diagram
CHARGE-CURRENT
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
100pF
RC
1M
RD
1500
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
IP 100%
90%
36.8%
tRL
TIME
tDL
CURRENT WAVEFORM
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
Ir
10%
0
AMPERES
CHARGE-CURRENT
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
150pF
RC
50M
to 100M
RD
330
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
Figure 3a. IEC 1000-4-2 ESD Test Model
Figure 2b. Human Body Model Current Waveform
Figure 2a. Human Body ESD Test Model
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