參數(shù)資料
型號: MAX3172
廠商: Maxim Integrated Products, Inc.
英文描述: Quad LVDS Receiver 16-TSSOP -40 to 85
中文描述: +3.3V、多協(xié)議、軟件可選的電纜端接器及收發(fā)器
文件頁數(shù): 15/19頁
文件大?。?/td> 276K
代理商: MAX3172
M
+3.3V Multiprotocol Software-Selectable
Cable Terminators and Transceivers
______________________________________________________________________________________
15
The MAX3174 does not have this glitch rejection and
can be operated at frequencies up to 240kbps if prop-
erly terminated.
DCE vs. DTE Operation
Figure 15 illustrates a DCE or DTE controller-selectable
interface. The DCE/
DTE
input switches the MAX3172/
MAX3174s
mode of operation. Logic high selects DCE,
which enables driver 4 on the MAX3172/MAX3174
(INVERT = 0), driver 3 on the MAX3171/MAX3173, and
driver 3 on the MAX3170. A logic low selects DTE,
which enables receiver 4 on the MAX3172/MAX3174
(INVERT = 0), receiver 1 on the MAX3171/MAX3173,
and receiver 1 on the MAX3170.
This application requires only one DB-25 connector.
See Figure 15 for complete signal routing in DCE and
DTE modes. For example, driver 4 routes the LL(DCE)
signal to pin 18 in DCE mode, while in DTE mode,
receiver 4 routes pin 18 to the LL(DTE) signal.
Complete Multiprotocol X.21 Interface
A complete DTE-to-DCE interface operating in X.21
mode is shown in Figure 16. The MAX3172/MAX3174 ter-
minate the V.11 clock and data signals, and its transceiv-
er carries the local loopback (LL) signal. The MAX3170
carries the clock and data signals, and the
MAX3171/MAX3173 carry the control signals. The control
signals generally do not require external termination.
Compliance Testing
A European Standard EN45001 test report is available
for the MAX3170
MAX3174 chipset. A copy of the test
report is available from Maxim upon request.
R6
10k
R8
5k
A
C
A
GND
R5
30k
R7
10k
R4
30k
MAX3172
MAX3174
S3
RECEIVER
Figure 14. V.10 Internal Resistance Networks
相關(guān)PDF資料
PDF描述
MAX3172CAI Quad LVDS Receiver 16-TSSOP -40 to 85
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