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參數(shù)資料
| 型號(hào)： | MAX3140EEI+T |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 34/36頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC UART W/RS485 28-QSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 特點(diǎn)： | 收發(fā)器 |
| FIFO's： | 8 字節(jié) |
| 規(guī)程： | RS232，RS485 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動(dòng)位檢測(cè)功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-QSOP |
| 供應(yīng)商設(shè)備封裝： | 28-QSOP |
| 包裝： | 帶卷 (TR) |
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MAX3140
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
_______________________________________________________________________________________
7
SWITCHING CHARACTERISTICS—SRL = GND
(VCC = +5V ±5%, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5V and TA = +25°C.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Driver Disable Time from Low
tDLZ
100
ns
Driver Enable to Output Low
tDZL
150
ns
Driver Enable to Output High
tDZH
150
ns
Maximum Data Rate
fMAX
10
Mbps
Driver Disable Time from High
tDHZ
100
ns
Receiver Input to Output
tRPLH,
tRPHL
106
150
ns
|tRPLH - tRPHL| Differential
Receiver Skew
tRSKD
0±10
ns
Receiver Enable to Output Low
tRZL
20
50
ns
Driver Output Skew
|tDPLH - tDPHL|
Driver Input to Output
tDPLH
34
60
ns
tDSKEW
-2.5
±10
ns
Driver Rise or Fall Time
tDR, tDF
14
25
ns
Receiver Enable to Output High
tRZH
20
50
ns
Receiver Disable Time from Low
tRLZ
20
50
ns
Receiver Disable Time from
High
tRHZ
20
50
ns
Time to Shutdown
tSHDN
50
200
600
ns
Driver Enable from Shutdown to
Output High
tDZH(SHDN)
250
ns
Driver Enable from Shutdown to
Output Low
tDZL(SHDN)
250
ns
Receiver Enable from Shutdown
to Output High
tRZH(SHDN)
3500
ns
34
60
CONDITIONS
Figures 2 and 8, CL = 100pF, S2 closed
Figures 4 and 6, CL = 15pF, S1 closed
Figures 2 and 8, CL = 100pF, S1 closed
Figures 4 and 6, CL = 100pF, S1 closed
Figures 4 and 6, CL = 100pF, S2 closed
Figures 4 and 6, CL = 15pF, S2 closed
Figures 7 and 9,
|VID| ≥ 2.0V,
rise and fall time of VID
≤ 15ns
Figures 2 and 8, CL = 100pF, S2 closed
(Note 5)
Figures 7 and 9,
|VID| ≥ 2.0V,
rise and fall time of VID
≤ 15ns
Figures 2 and 8, CL = 100pF, S1 closed
Figures 4 and 6, CL = 15pF, S2 closed
Figures 4 and 6, CL = 15pF, S1 closed
Figures 2 and 8, CL = 100pF, S2 closed
Figures 3 and 5, RDIFF = 54
Ω,
CL1 = CL2 = 100pF
Receiver Enable from Shutdown
to Output Low
Figures 3 and 5, RDIFF = 54
Ω,
CL1 = CL2 = 100pF
tRZL(SHDN)
3500
Figures 3 and 5, RDIFF = 54
Ω,
CL1 = CL2 = 100pF
ns
Figures 2 and 8, CL = 100pF, S1 closed
tDPHL
Note 1: All currents into the device are positive; all currents out of the device are negative. All voltages are referred to device
ground unless otherwise noted.
Note 2:
ΔVOD and ΔVOC are the changes in VOD and VOC, respectively, when the Dl input changes state.
Note 3: The SRL pin is internally biased to VCC/2 by a 100k
Ω/100kΩ resistor-divider. It is guaranteed to be VCC/2 if left unconnected.
Note 4: Maximum current level applies to peak current just prior to foldback-current limiting; minimum current level applies during
current limiting.
Note 5: The device is put into shutdown by bringing RE high and DE low. If the enable inputs are in this state for less than 50ns, the
device is guaranteed not to enter shutdown. If the enable inputs are in this state for at least 600ns, the device is guaranteed
to have entered shutdown.
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