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參數(shù)資料
| 型號： | MAX3140CEI+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 14/36頁 |
| 文件大小： | 0K |
| 描述： | IC UART W/RS485 28-QSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 特點(diǎn)： | 收發(fā)器 |
| FIFO's： | 8 字節(jié) |
| 規(guī)程： | RS232，RS485 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-QSOP |
| 供應(yīng)商設(shè)備封裝： | 28-QSOP |
| 包裝： | 帶卷 (TR) |
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MAX3140
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
______________________________________________________________________________________
21
Table 4. WRITE DATA Register Bit Assignment (D15, D14 = 1, 0)
14
0
T
6
D6t
D6r
7
D7t
D7r
15
2
DIN
1
D2t
DOUT
R
D2r
BIT
3
D3t
D3r
0
D0t
D0r
1
D1t
D1r
4
D4t
D4r
5
D5t
D5r
10
TE
RA/FE
11
0
8
Pt
Pr
9
RTS
CTS
12
0
13
0
Notes:
5, 14: DIN
1, 0 = Write Data
bit 13–11: DIN
Zeros
bit 10: DIN
TE = 1, Disables transmit, and only RTS will be updated.
TE = 0, Enables transmit.
bit 9: DIN
RTS = 1, Configures RTS = 0 (Logic Low).
RTS = 0, Configures RTS = 1 (Logic High).
bit 8: DIN
Pt = 1, Transmit parity bit is high. If PE = 1, a high parity bit will
be transmitted. If PE = 0, then no parity bit will be transmitted.
Pt = 0, Transmit parity bit is low. If PE = 1, a low parity bit will be
transmitted. If PE = 0, then no parity bit will be transmitted.
bit 7–0: DIN
D7t–D0t = Transmitting Data bits. D7t is ignored when L = 1.
bit 15: DOUT
R = 1, Data is available to be read from the receive register or
FIFO.
R = 0, Receive register and FIFO are empty.
bit 14: DOUT
T = 1, Transmit buffer is empty.
T = 0, Transmit buffer is full.
bit 13–11: DOUT
Zeros
bit 10: DOUT
RA/FE = Receive-activity (UART shutdown)/Framing-error
(normal operation) bit.
bit 9: DOUT
CTS = CTS input state. If CTS = 0, then CTS = 1 and vice versa.
bit 8: DOUT
Pr = Received parity bit. This is only valid if PE = 1.
bit 7–0: DOUT
D7t–D0t = Received Data bits. D7r = 0 for L = 1.
Test Mode
The device enters a test mode if bit 0 of the DIN config-
uration word equals 1 when performing a READ CON-
FIGURATION. In this mode, if CS = 0, the RTS pin
transmits a clock that is 16 times the baud rate. The TX
pin is low as long as CS remains low while in test mode.
Table 3 shows the bit assignment for the READ CON-
FIGURATION register.
WRITE DATA Register (D15, D14 = 1, 0)
Use the WRITE DATA register for transmitting to the TX
buffer and receiving from the RX buffer (and RX FIFO
when enabled). When using this register, the DIN and
DOUT WRITE DATA words are used simultaneously
and bits 13–11 for both the DIN and DOUT WRITE
DATA words are meaningless zeros. The DIN WRITE
DATA word contains the data that is being transmitted,
and the DOUT WRITE DATA word contains the data
that is being received from the RX FIFO. Table 4 shows
the bit assignment for the WRITE DATA register. To
change the RTS pin’s output state without transmitting
data, set the TE bit high. If performing a WRITE DATA
operation, the R bit clears on the falling edge of SCLK’s
16th clock pulse if no new data is available.
READ DATA Register (D15, D14 = 0, 0)
Use the READ DATA register for receiving data from
the RX FIFO. When using this register, bits 15 and 14 of
DIN must both be 0. Clear bits 13–0 of the DIN READ
DATA word. Table 5 shows the bit assignments for the
READ DATA register. Reading all available data clears
the R bit and interrupt IRQ. If performing a READ DATA
operation, the R bit clears on the falling edge of SCLK’s
16th clock pulse if no new data is available.
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