參數(shù)資料
型號: MAX3109ETJ+
廠商: Maxim Integrated Products
文件頁數(shù): 32/66頁
文件大?。?/td> 0K
描述: SEMICONDUCTOR OTHER
標準包裝: 60
系列: *
Dual Serial UART with 128-Word FIFOs
MAX3109
38
Maxim Integrated
MODE1 Register
Bit 6: AutoSleep
Set the AutoSleep bit high to set the MAX3109 to automatically enter low-power sleep mode after a period of no activity
(see the Auto-Sleep Mode section). An interrupt is generated in STSInt[6]: SleepInt when the MAX3109 enters sleep
mode.
Bit 5: ForcedSleep
Set the ForcedSleep bit high to force the MAX3109 into low-power sleep mode (see the Forced-Sleep Mode section).
The current sleep state can be read out through the ForcedSleep bit, even when the UART is in sleep mode.
Bit 4: TrnscvCtrl
Set the TrnscvCtrl bit high to enable auto transceiver direction control mode. RTS_ automatically controls the trans-
ceiver’s transmit/receive enable/disable inputs in this mode. RTS_ is logic-low so that the transceiver is in receive
mode with the transmitter disabled until the TxFIFO contains data available for transmission, at which point RTS_ is
automatically set logic-high before the transmitter sends out the data. Once the transmitter is empty, RTS_ is automati-
cally forced low again.
Setup and hold times for RTS_ with respect to the TX_ output can be defined through the HDplxDelay register. A
transmitter empty interrupt is generated in ISR[5] when the TxFIFO is empty.
Bit 3: RTSHiZ
Set the RTSHiZ bit high to three-state RTS_.
Bit 2: TxHiZ
Set the TxHiZ bit high to three-state the TX_ output.
Bit 1: TxDisabl
Set the TxDisabl bit high to disable transmission. If the TxDisabl bit is set high during transmission, the transmitter com-
pletes sending out the current character and then ceases transmission. Data still present in the transmit FIFO remains
in the TxFIFO. The TX_ output is set to logic-high after transmission.
In auto transceiver direction control mode, TxDisabl is high when the transmitter is completely empty.
Bit 0: RxDisabl
Set the RxDisabl bit high to disable the receiver of the selected UART so that the receiver stops receiving data. All data
present in the receive FIFO remains in the RxFIFO.
ADDRESS:
0x09
MODE:
R/W
BIT
7
6
5
4
3
2
1
0
NAME
AutoSleep
ForcedSleep
TrnscvCtrl
RTSHiZ
TxHiZ
TxDisabl
RxDisabl
RESET
0
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