SPI/I2C UART with 128-Word FIFOs Crystal Oscillator Set CLKSource[4]: ClockEn to" />
參數(shù)資料
型號(hào): MAX3107EAG+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 9/52頁(yè)
文件大?。?/td> 0K
描述: IC UART SPI/I2C 128 FIFO 24SSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
特點(diǎn): 內(nèi)部振蕩器
通道數(shù): 4,QUART
FIFO's: 128 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.35 V ~ 3.6 V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 24-SSOP
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: MAX3107EAG+TDKR
SPI/I2C UART with 128-Word FIFOs
Crystal Oscillator
Set CLKSource[4]: ClockEn to 1 and CLKSource[1]:
CrystalEn to 1 to enable and select the crystal oscilla-
tor. The on-chip crystal oscillator has load capacitances
of 20pF integrated in both XIN and XOUT. Connect an
external crystal or ceramic oscillator between XIN and
XOUT.
External Clock Source
When an external clock signal is used, this should
be connected to XIN. Leave XOUT unconnected.
Set CLKSource[4]: ClockEn to 1 and CLKSource[1]:
CrystalEn to 0 to select external clocking.
PLL and Predivider
The internal predivider and PLL allow for a wide range
of external clock frequencies and baud rates. The PLL
can be configured to multiply the input clock rate by a
factor of 6, 48, 96, or 144 through PLLConfig[7:6]. The
predivider, located between the input clock and the PLL,
allows division of the input clock by a factor between 1
and 63 by writing to PLLConfig[5:0]. See the PLLConfig
register description for more information.
Fractional Baud-Rate Generator
The internal fractional baud-rate generator provides a
high degree of flexibility and high resolution in baud-
rate programming. The baud-rate generator has a 16-bit
integer divisor and a 4-bit word for the fractional divisor.
The fractional baud-rate generator can be used with the
external crystal or clock source.
The integer and fractional divisors are calculated through
the divisor, D:
REF
f
D
16 BaudRate
=
×
where fREF is the reference frequency input to the baud-
rate generator and D is the ideal divisor. fREF must be
less than 96MHz. In 2x and 4x rate modes, replace the
divisor 16 by 8 or 4, respectively.
The integer divisor portion, DIV, of the divisor, D, is
obtained by truncating D:
DIV = TRUNC(D)
Figure 6. Receive FIFO
Figure 7. Clock Selection Diagram
RECEIVE FIFO
FIFOTrgLvl[7:4]
TRIGGER
ISR[3]
WORD
ERROR 128
RxFIFOLvl
4
3
2
1
TIMEOUT
EMPTY
ERRORS
OVERRUN
LSR[1]
RECEIVED
DATA
RHR
RECEIVER
RX
I2C/SPI INTERFACE
LSR[0]
ISR[6]
LSR[5:2]
CURRENT FILL LEVEL
CRYSTAL
OSCILLATOR
XOUT
CrystalEn
XIN
BAUD-RATE
GENERATOR
ClockEn
PLLByps
PLLEn
PLL
DIVIDER
Maxim Integrated
17
MAX3107
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