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參數(shù)資料
| 型號： | MAX3100ETG+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 2/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART SPI/MICROWIRE 24-TQFN-EP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 特點： | 低功率 |
| 通道數(shù)： | 1，UART |
| FIFO's： | 8 字節(jié) |
| 規(guī)程： | RS232，RS485 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 24-TQFN-EP（4x4） |
| 包裝： | 帶卷 (TR) |
Table 5. Bit Descriptions (continued)
SPI/MICROWIRE-Compatible
UART in QSOP-16
POR
STATE
DESCRIPTION
READ/
WRITE
BIT
NAME
0
SHDNi
w
Software-Shutdown Bit. Enter software shutdown with a write configuration where SHDNi = 1.
Software shutdown takes effect after CS goes high, and causes the oscillator to stop as soon
as the transmitter becomes idle. Software shutdown also clears R, T, RA/FE, D0r–D7r,
D0t–D7t, Pr, Pt, and all data in the receive FIFO. RTS and CTS can be read and updated
while in shutdown. Exit software shutdown with a write configuration where SHDNi = 0. The
oscillator restarts typically within 50ms of CS going high. RTS and CTS are unaffected. Refer
to the
Pin Description for hardware shutdown (SHDN input).
0
SHDNo
r
Shutdown Read-Back Bit. The read-configuration register outputs SHDNo = 1 when the UART
is in shutdown. Note that this bit is not sent until the current byte in the transmitter is sent (T =
1). This tells the processor when it may shut down the RS-232 driver. This bit is also set imme-
diately when the device is shut down through the SHDN pin.
0
RA/FE
r
Receiver-Activity/Framing-Error Bit. In shutdown mode, this is the RA bit. In normal operation,
this is the FE bit. In shutdown mode, a transition on RX sets RA = 1. In normal mode, a fram-
ing error sets FE = 1. A framing error occurs if a zero is received when the first stop bit is
expected. FE is set when a framing error occurs, and cleared upon receipt of the next proper-
ly framed character independent of the FIFO being enabled. When the device wakes up, it is
likely that a framing error will occur. This error can be cleared with a write configuration. The
FE bit is not cleared on a Read Data operation. When an FE is encountered, the UART resets
itself to the state where it is looking for a start bit.
0
ST
w
Transmit-Stop Bit. One stop bit will be transmitted when ST = 0. Two stop bits will be transmit-
ted when ST = 1. The receiver only requires one stop bit.
0
ST
r
Reads the value of the ST bit.
0
TM
w
Mask for T bit. IRQ is asserted if TM = 1 and T = 1 (Table 6).
0
TM
r
Reads the value of the TM bit (Table 6).
1
T
r
Transmit-Buffer-Empty Flag. T = 1 means that the transmit buffer is empty and ready to
accept another data word.
0
TE
w
Transmit-Enable Bit. If TE = 1, then only the RTS pin will be updated on CS’s rising edge. The
contents of RTS, Pt, and D0t–D7t transmit on CS’s rising edge when TE = 0.
IDLE
SECOND STOP BIT IS OMITTED IF ST = 0.
PE = 1, L = 1
TIME
D0
START
D1
D2
D3
D4
D5
D6
Pt
STOP
IDLE
PE = 1, L = 0
D0
START
D1
D2
D3
D4
D5
D6
D7
Pt
STOP
IDLE
PE = 0, L = 1
D0
START
D1
D2
D3
D4
D5
D6
STOP
IDLE
PE = 0, L = 0
D0
START
D1
D2
D3
D4
D5
D6
D7
STOP
IDLE
Figure 5. Parity and Word-Length Control
MAX3100
10
Maxim Integrated
MAX3100
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