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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | MAX3100CEE+T |
| 寤犲晢锛� | Maxim Integrated Products |
| 鏂囦欢闋佹暩(sh霉)锛� | 7/24闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC UART SPI COMPAT 16-QSOP |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 2,500 |
| 鐗归粸锛� | 浣庡姛鐜� |
| 閫氶亾鏁�(sh霉)锛� | 1锛孶ART |
| FIFO's锛� | 8 瀛楃瘈(ji茅) |
| 瑕�(gu墨)绋嬶細 | RS232锛孯S485 |
| 闆绘簮闆诲锛� | 2.7 V ~ 5.5 V |
| 甯禝rDA 绶ㄧ⒓鍣�/瑙ｇ⒓鍣細 | 鏄� |
| 甯舵晠闅滃暉鍕曚綅妾㈡脯鍔熻兘锛� | 鏄� |
| 甯禖MOS锛� | 鏄� |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 16-SSOP锛�0.154"锛�3.90mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 16-QSOP |
| 鍖呰锛� | 甯跺嵎 (TR) |
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The MAX3100 X1 input can be driven directly by an
external CMOS clock source. The trip level is approxi-
mately equal to VCC / 2. No connection should be made
to X2 in this mode. If a TTL or non-CMOS clock source
is used, AC couple with a 10nF capacitor to X1. The
peak-to-peak swing on the input should be at least 2V
for reliable operation.
9-Bit Networks
The MAX3100 supports a common multidrop communi-
cation technique referred to as 9-bit mode. In this mode,
the parity bit is set to indicate a message that contains a
header with a destination address. The MAX3100 parity
mask can be set to generate interrupts for this condition.
Operating a network in this mode reduces the process-
ing overhead of all nodes by enabling the slave con-
trollers to ignore most message traffic. This can relieve
the remote processor to handle more useful tasks.
In 9-bit mode, the MAX3100 is set up with 8 bits plus
parity. The parity bit in all normal messages is clear, but
is set in an address-type message. The MAX3100 pari-
ty-interrupt mask is enabled to generate an interrupt on
high parity. When the master sends an address mes-
sage with the parity bit set, all MAX3100 nodes issue an
interrupt. All nodes then retrieve the received byte to
compare to their assigned address. Once addressed,
the node continues to process each received byte. If the
node was not addressed, it ignores all message traffic
until a new address is sent out by the master.
The parity/9th-bit interrupt is controlled only by the data
in the receive register, and is not affected by data in the
FIFO, so the most effective use of the parity/9th-bit
interrupt is with FIFO disabled. With the FIFO disabled,
received nonaddress words can be ignored and not
even read from the UART.
SIR IrDA Mode
The MAX3100鈥檚 IrDA mode can be used to communicate
with other IrDA SIR-compatible devices, or to reduce
power consumption in opto-isolated applications.
In IrDA mode, a bit period is shortened to 3/16 of a
baud period (1.6s at 115,200 baud) (Figure 9). A data
zero is transmitted as a pulse of light (TX pin = logic
low, RX pin = logic high).
In receive mode, the RX signal鈥檚 sampling is done
halfway into the transmission of a high level. The sam-
pling is done once, instead of three times, as in normal
mode. The MAX3100 ignores pulses shorter than
approximately 1/16 of the baud period. The IrDA device
that is communicating with the MAX3100 must be set to
transmit pulses at 3/16 of the baud period. For compati-
bility with other IrDA devices, set the format to 8-bit
data, one stop, no parity.
IrDA Module
The MAX3100 was optimized for direct optocoupler
drive, whereas IrDA modules contain inverting buffers.
Invert the RX and TX outputs as shown in Figure 10.
8051 Example: IrDA to RS-232 Converter
Figure 10 shows the MAX3100 with an 8051 C. This
circuit receives IrDA data and outputs standard RS-232
data. Although the 8051 contains an internal UART, it
does not support IrDA or high-speed communications.
The MAX3100 can easily interface to the 8051 to sup-
port these high-performance communications modes.
The 8051 does not have an SPI interface, so communi-
cation with the MAX3100 is accomplished with port pins
and a short software routine (Figure 12a).
The software routine polls the IRQ output to see if data
is available from the MAX3100 UART. It then shifts the
data out, using the 8051 port pins, and transmits it out
the RS-232 side through the MAX3221 driver. The 8051
simultaneously monitors its internal UART for incoming
communications from the RS-232 side, and transmits
this data out the IrDA side through the MAX3100. The
low-level routine (UTLK) is the core routine that sends
and receives data over the port pins to simulate an SPI
port on the 8051. This technique is useful for any 8051-
based MAX3100 port-pin-interfaced application.
SPI/MICROWIRE-Compatible
UART in QSOP-16
START
STOP
START
STOP
NORMAL
RX
UART FRAME
DATA BITS
01
1
00
0
NORMAL UART
TX
11
1
00
0
IrDA
RX
IrDA
TX
Figure 9. IrDA Timing
MAX3100
Maxim Integrated
15
MAX3100
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| MAX3100CEE-T | IC UART SPI/MICRWIRE COMP 16QSOP |
| MAX3100CEE | IC UART SPI/MICRWIRE COMP 16QSOP |
| IS82C52 | IC PERIPH UART/BRG 16MHZ 28-PLCC |
| IP82C52 | IC UART/BRG PERIPHERAL 28-DIP |
| ID82C52 | IC UART/BRG 5V 16MHZ 28-DIP |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| MAX3100CPD | 鍔熻兘鎻忚堪:UART 鎺ュ彛闆嗘垚闆昏矾 RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 鏁�(sh霉)鎿�(j霉)閫熺巼:3 Mbps 闆绘簮闆诲-鏈€澶�:3.6 V 闆绘簮闆诲-鏈€灏�:2.7 V 闆绘簮闆绘祦:20 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽 / 绠遍珨:LQFP-48 灏佽:Reel |
| MAX3100CPD+ | 鍔熻兘鎻忚堪:UART 鎺ュ彛闆嗘垚闆昏矾 SPI/uWire Compatible RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 鏁�(sh霉)鎿�(j霉)閫熺巼:3 Mbps 闆绘簮闆诲-鏈€澶�:3.6 V 闆绘簮闆诲-鏈€灏�:2.7 V 闆绘簮闆绘祦:20 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽 / 绠遍珨:LQFP-48 灏佽:Reel |
| MAX3100EEE | 鍔熻兘鎻忚堪:UART 鎺ュ彛闆嗘垚闆昏矾 RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 鏁�(sh霉)鎿�(j霉)閫熺巼:3 Mbps 闆绘簮闆诲-鏈€澶�:3.6 V 闆绘簮闆诲-鏈€灏�:2.7 V 闆绘簮闆绘祦:20 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽 / 绠遍珨:LQFP-48 灏佽:Reel |
| MAX3100EEE+ | 鍔熻兘鎻忚堪:UART 鎺ュ彛闆嗘垚闆昏矾 SPI/uWire Compatible RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 鏁�(sh霉)鎿�(j霉)閫熺巼:3 Mbps 闆绘簮闆诲-鏈€澶�:3.6 V 闆绘簮闆诲-鏈€灏�:2.7 V 闆绘簮闆绘祦:20 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽 / 绠遍珨:LQFP-48 灏佽:Reel |
| MAX3100EEE+T | 鍔熻兘鎻忚堪:UART 鎺ュ彛闆嗘垚闆昏矾 SPI/uWire Compatible RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 鏁�(sh霉)鎿�(j霉)閫熺巼:3 Mbps 闆绘簮闆诲-鏈€澶�:3.6 V 闆绘簮闆诲-鏈€灏�:2.7 V 闆绘簮闆绘祦:20 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽 / 绠遍珨:LQFP-48 灏佽:Reel |
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