參數(shù)資料
型號: MAX2105
廠商: Maxim Integrated Products, Inc.
英文描述: 16-Bit Buffers/Drivers With 3-State Outputs 48-TSSOP -40 to 85
中文描述: 直接變頻調(diào)諧器IC,適合數(shù)字DBS應(yīng)用
文件頁數(shù): 9/16頁
文件大小: 151K
代理商: MAX2105
M
Direc t-Conversion Tuner ICs for
Digital DBS Applic ations
_______________________________________________________________________________________
9
Pin Desc ription
RF Ground. Connect directly to the ground plane.
GND
9, 11,
19, 24
Automatic Gain-Control Input. Bypass this pin with a 1000pF capacitor close to the pin, to minimize cou-
pling.
AGC
10
Q Channel Baseband Output
QOUT
13
Baseband +5V Supply. Bypass with a 10pF capacitor from this pin to pin 12 (GND), as close to the IC as
possible. Connect an additional 0.1μF capacitor in parallel with the 10pF capacitor (placement less critical).
V
CC
14
Q Channel Offset-Correction Noninverting Input. Connect a 0.22μF (typ) capacitor between QDC and
QDC
.
This capacitor must be placed as close to the IC as possible (see Layout Considerations section).
QDC
15
Ground (substrate)
GND
5
RF +5V Supply. Bypass with a 22pF capacitor from this pin to pin 9 (GND), as close to the IC as possible.
V
CC
RFIN
6
RF Noninverting Input. Couple through a 22pF capacitor directly to a 50
signal source.
RF Inverting Input. Connect to a 22pF series capacitor and a 51
resistor to ground.
7
RFIN
8
RF +5V Supply. Bypass with a 22pF capacitor from this pin to pin 11 (GND), as close to the IC as possible.
V
CC
4
Baseband Ground
GND
3, 12
PIN
I Channel Baseband Output
IOUT
2
Baseband +5V Supply. Bypass with a 10pF capacitor from this pin to pin 3 (GND), as close to the IC as
possible. Connect an additional 0.1μF capacitor in parallel with the 10pF capacitor (placement less critical).
V
CC
1
FUNCTION
NAME
Q Channel Offset-Correction Inverting Input. Connect a 0.22μF (typ) capacitor between QDC and
QDC
. This
capacitor must be placed as close to the IC as possible (see Layout Considerations section).
QDC
16
I Channel Offset-Correction Inverting Input. Connect a 0.22μF (typ) capacitor between IDC and
IDC
. This
capacitor must be placed as close to the IC as possible (see Layout Considerations section).
IDC
17
I Channel Offset-Correction Noninverting Input. Connect a 0.22μF (typ) capacitor between IDC and
IDC
.
This capacitor must be placed as close to the IC as possible (see Layout Considerations section).
IDC
18
RF +5V Supply. Bypass with a 10pF capacitor from this pin to pin 19 (GND) as close to the IC as possible.
V
CC
20
Local-Oscillator Complementary Input Port (Figure 1)
LO
21
Local-Oscillator Input Port (Figure 1)
LO
22
RF +5V Supply. Bypass with a 10pF capacitor from this pin to pin 24 (GND) as close to the IC as possible.
V
CC
23
Prescaler Ground. To disable the prescaler, leave this pin open.
PSGND
25
Prescaler Output. Drives CMOS load. Connect 2k
from this pin to GND (if the prescaler is enabled).
PSOUT
26
Prescaler Modulus Control. Leave open when the prescaler is disabled.
MOD
27
Prescaler +5V Supply.
Must be connected even if the prescaler is disabled.
Bypass with a 1000pF
capacitor.
V
CC
28
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