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參數(shù)資料
| 型號： | MAX2100 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Quadrature Digitizer Circuits(正交數(shù)字轉(zhuǎn)換器電路) |
| 中文描述： | 正交數(shù)字轉(zhuǎn)換電路（正交數(shù)字轉(zhuǎn)換器電路） |
| 文件頁數(shù)： | 4/8頁 |
| 文件大小： | 72K |
| 代理商： | MAX2100 |
M
Dual 6-Bit ADCs (Megac ell)
4
_______________________________________________________________________________________
____________________________Features
o
Dual, 6-Bit, 120Msps Flash Architecture
o
Programmable Sample Rate
o
Excellent Dynamic Performance
(5.8 effective bits at f
IN
= 30MHz)
o
Low Incidence of Metastable States
o
All Reference Generation Circuitry Included
_________________________Desc ription
The X2113 “Megacell” contains two 6-bit flash ADCs and
associated reference and clock generation circuitry. The
comparator array in each ADC contains 63 identical dif-
ferential comparator and latch cells. The proprietary dif-
ferential architecture minimizes integral linearity error and
the occurrence of metastable states. The thermometer
code output of the comparator array is translated into
gray code using a fully differential wired-AND/wired-OR
scheme. This maximizes noise immunity. The gray code
is then converted to binary with a modified XOR array.
The reference generator applies a precision bandgap
signal to the differential ladder in the comparator array.
Additional circuitry is provided to adjust the half-scale
ladder voltage to the common-mode voltage of the dif-
ferential input signal.
A programmable divider allows the user to change
sample rate from a fixed external-clock oscillator.
Cell Dimensions: 2800μm x 1500μm
6
6
QOUTPUT
REF OUT
SAMPLE RATE
QINPUT
CLOCK IN
I INPUT
CLOCK OUT
I OUTPUT
3
X2113
/N
ADC
ADC
REF
GEN
X2113 DUAL 6-BIT ADCs
(MEGACELL)
KEY ELECTRICAL CHARACTERISTICS
(T
A
= 0°C to +70°C, unless otherwise noted.)
_____________________Bloc k Diagram
k
pF
dB
ps
5
RIN
CIN
A
Input Resistance
Input Capacitance
Amplitude Response Mismatch
Aperture Uncertainty
2
f
IN
= 30MHz, f
S
= 60Msps, 95% FS
f1 = 10MHz, FS–7dB; f2 = 12MHz, FS–7dB
Full-scale to <1%
CONDITIONS
MHz
Bits
dBc
ns
V
20
BW0.1dB
ENOB
IM3
t
TRAN
VIN
FS
0.1dB Bandwidth
Effective Number of Bits
Input Third-Order Intermod
Settling Time
Full-Scale Input Range
Msps
120
SRmax
Maximum Sample Rate,
Each Channel
V
2.25
2.75
VIN
cm
Common-Mode Input Range
5.8
-38
10
±0.75
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
Channel-to-channel
f
S
= 60Msps
ps
20
Aperture Delay Match,
Channel-to-Channel
0.3
80
V
CC
= 5.0V ±5%
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