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參數(shù)資料
| 型號(hào)： | MAX199BMYI |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | Multi-Range (【4V, 【2V, +4V, +2V), +5V Supply, 12-Bit DAS with 8+4 Bus Interface |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, CDIP28 |
| 封裝： | 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-28 |
| 文件頁(yè)數(shù)： | 8/16頁(yè) |
| 文件大?。?/td> | 165K |
| 代理商： | MAX199BMYI |
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M
Multi-Range (±4V, ±2V, +4V, +2V ),
+5V S upply, 12-Bit DAS with 8+4 Bus Interfac e
8
_______________________________________________________________________________________
_______________Detailed Desc ription
Converter Operation
The MAX199, a multi-range, fault-tolerant ADC, uses
successive approximation and internal input track/hold
(T/H) circuitry to convert an analog signal to a 12-bit
digital output. The parallel-output format provides easy
interface to microprocessors (μPs). Figure 3 shows the
MAX199 in its simplest operational configuration.
Analog-Input T rac k/Hold
In the internal acquisition control mode (control bit D5
set to 0), the T/H enters its tracking mode on WR’s ris-
ing edge, and enters its hold mode when the internally
timed (6 clock cycles) acquisition interval ends. In bipo-
lar mode, a low-impedance input source, which settles
in less than 1.5μs, is required to maintain conversion
accuracy at the maximum conversion rate.
When configured for unipolar mode, the input does not
need to be driven from a low-impedance source. The
acquisition time (t
AZ
) is a function of the source output
resistance (R
S
), the channel input resistance (R
IN
), and
the T/H capacitance.
Acquisition time is calculated by:
For 0V to V
REF
: t
AZ
= 9 x (R
S
+ R
IN
) x 16pF
For 0V to V
REF/2
: t
AZ
= 9 x (R
S
+ R
IN
) x 32pF
where R
IN
= 7k
, and t
AZ
is never less than 2μs (0V to
V
REF
range) or 3μs (0V to V
REF/2
range).
In the external acquisition control mode (D5 = 1), the
T/H enters its tracking mode on the first WR rising edge
and enters its hold mode when it detects the second WR
rising edge with D5 = 0. See the External Acquisition
section.
Input Bandwidth
The ADC’s input tracking circuitry has a 5MHz small-
signal bandwidth. When using the internal acquisition
mode with an external clock frequency of 2MHz, a
100ksps throughput rate can be achieved. It is possible
to digitize high-speed transient events and measure
periodic signals with bandwidths exceeding the ADC’s
sampling rate by using undersampling techniques. To
avoid high-frequency signals being aliased into the fre-
quency band of interest, anti-alias filtering is recom-
mended (MAX274/MAX275 continuous-time filters).
Input Range and Protec tion
Figure 4 shows the equivalent input circuit. The MAX199
can be programmed for input ranges of ±V
REF
, ±V
REF/2
,
0V to V
REF
, or 0V to V
REF/2
by setting the appropriate
control bits (D3, D4) in the control byte (see Tables 1 and
2). When an external reference is applied at REFADJ , the
voltage at REF is given by V
REF
= 1.6384 x V
REFADJ
(2.4V
< V
REF
< 4.18V).
DGND
V
DD
REF
REFADJ
INT
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
AGND
28
27
26
25
4.7
μ
F
0.1
μ
F
+5V
+4.096V
OUTPUT STATUS
24
23
22
21
20
19
18
17
16
1
2
μ
P
CONTROL
INPUTS
3
4
5
6
7
CLK
CS
WR
RD
HBEN
SHDN
D7
D6
D5
D4
D3/D11
D2/D10
D1/D9
D0/D8
100pF
μ
P DATA BUS
15
8
9
10
11
12
13
14
ANALOG
INPUTS
MAX199
Figure 3. Operational Diagram
5.12k
5.12k
CH_
S1
S2
S3
S4
BIPOLAR
UNIPOLAR
VOLTAGE
REFERENCE
T/H
OUT
HOLD
TRACK
TRACK
HOLD
OFF
ON
C
HOLD
S1 = BIPOLAR/UNIPOLAR SWITCH
S2 = INPUT MUX SWITCH
S3, S4 = T/H SWITCH
Figure 4. Equivalent Input Circuit
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