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參數(shù)資料
| 型號(hào)： | MAX199BEWI+T |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 16/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAS 12BIT 8CH 28-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 數(shù)據(jù)采集系統(tǒng)（DAS） |
| 分辨率（位）： | 12 b |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 電壓電源： | 單電源 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
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The input channels are overvoltage protected to
±16.5V. This protection is active even if the device is in
power-down mode.
Even with VDD = 0V, the input resistive network provides
current-limiting that adequately protects the device.
Digital Interface
Input data (control byte) and output data are multiplexed
on a three-state parallel interface. This parallel I/O can
easily be interfaced with a P. CS, WR, and RD control
the write and read operations. CS is the standard chip-
select signal, which enables a P to address the MAX199
as an I/O port. When high, it disables the WR and RD
inputs and forces the interface into a high-Z state.
Input Format
The control byte is latched into the device, on pins
D7–D0, during a write cycle. Table 1 shows the control-
byte format.
Output Data Format
The output data format is binary in unipolar mode and
twos-complement binary in bipolar mode. When read-
ing the output data, CS and RD must be low. When
HBEN is low, the lower eight bits are read. When HBEN
is high, the upper four MSBs are available and the out-
put data bits D4–D7 are either set low (in unipolar
mode) or set to the value of the MSB (in bipolar mode)
(Table 5).
MAX199
Multi-Range (±4V, ±2V, +4V, +2V),
+5V Supply, 12-Bit DAS with 8+4 Bus Interface
_______________________________________________________________________________________
9
Table 1. Control-Byte Format
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
PD1
PD0
ACQMOD
RNG
BIP
A2
A1
A0
Table 3. Clock and Power-Down Selection
PD1 PD0
DEVICE MODE
0
Normal Operation / External Clock Mode
0
1
Normal Operation / Internal Clock Mode
1
0
Standby Power-Down (STBYPD); clock mode
is unaffected
1
Full Power-Down (FULLPD); clock mode is
unaffected
Table 2. Range and Polarity Selection
BIP
RNG
INPUT RANGE (V)
0
0 to VREF/2
0
1
0 to VREF
1
0
±VREF/2
1
±VREF
Table 4. Channel Selection
A2
A1
A0
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
0
0
1
0
1
0
0
1
1
0
1
0
1
1
0
1
BIT
NAME
DESCRIPTION
7, 6
PD1, PD0
These two bits select the clock and power-down modes (Table 3).
5
ACQMOD
0 = internally controlled acquisition (6 clock cycles), 1 = externally controlled acquisition
4
RNG
Selects the full-scale voltage magnitude at the input (Table 2).
3
BIP
Selects unipolar or bipolar conversion mode (Table 2).
2, 1, 0
A2, A1, A0
These are address bits for the input mux to select the “on” channel (Table 4).
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