M
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
______________________________________________________________________________________
45
When working with low-input voltages, the duty-factor limit
must be calculated using worst-case values for on- and
off-times. Manufacturing tolerances and internal propaga-
tion delays introduce an error to the TON K factor. This
error is greater at higher frequencies (Table 3).
Also, keep in mind that transient response performance
of buck regulators operated close to dropout is poor,
and bulk output capacitance must often be added (see
the V
SAG
equation in the
Design Procedure
section).
The absolute point of dropout is when the inductor cur-
rent ramps down during the minimum off-time (
I
DOWN
)
as much as it ramps up during the on-time (
I
UP
). The
ratio h =
I
UP
/
I
DOWN
is an indicator of ability to slew
the inductor current higher in response to increased
load, and must always be greater than 1. As h
approaches 1, the absolute minimum dropout point, the
inductor current is less able to increase during each
switching cycle and V
SAG
greatly increases, unless
additional output capacitance is used.
A reasonable minimum value for h is 1.5, but this can
be adjusted up or down to allow trade-offs between
V
SAG
, output capacitance, and minimum operating volt-
age. For a given value of h, the minimum operating volt-
age can be calculated as:
where V
DROP1
and V
DROP2
are the parasitic voltage
drops in the discharge and charge paths, respectively
(see the
On-Time One-Shot (TON)
section), T
OFF(MIN)
is from the
Electrical Characteristics
table, and K is
taken from Table 3. The absolute minimum input volt-
age is calculated with h = 1.
If the calculated V
IN(MIN)
is greater than the required
minimum input voltage, then operating frequency must
be reduced or output capacitance added to obtain
an acceptable V
SAG
. If operation near dropout is
anticipated, calculate V
SAG
to be sure of adequate
transient response.
Dropout Design Example
V
OUT
= 1.2V
f
SW
= 300kHz
K = 3.3μs, worst-case K = 2.97μs
T
OFF(MIN)
= 500ns
V
DROP1
= V
DROP2
= 100mV
h = 1.5
Calculate again with h = 1 gives the absolute limit of
dropout:
Since 1.56V is less than the lower limit of the input volt-
age range (2V), the practical minimum input voltage
with reasonable output capacitance would be 2V.
One-Stage (Battery Input) vs.
Two-Stage (5V Input) Conversion
The MAX1816/MAX1994 can be used with a direct bat-
tery connection (one stage) or can obtain power from a
regulated 5V supply (two stage). Each approach has
advantages, and careful consideration should go into
the selection of the final design.
The one-stage approach offers smaller total inductor
size and fewer capacitors overall due to the reduced
demands on the 5V supply. The transient response of
the single stage is better due to the ability to ramp up
the inductor current faster. The total efficiency of a sin-
gle stage is better than the two-stage approach.
The two-stage approach allows flexible placement due
to smaller circuit size and reduced local power dissipa-
tion. The power supply can be placed closer to the
CPU for better regulation and lower I
2
R losses from PC
board traces. Although the two-stage design has worse
transient response than the single stage, this can be
offset by the use of a voltage-positioned converter.
Ceramic Output Capacitor Applications
Ceramic capacitors have advantages and disadvan-
tages. They have ultra-low ESR and are noncom-
bustible, relatively small, and nonpolarized. They are
also expensive and brittle, and their ultra-low ESR char-
acteristic can result in excessively high ESR zero fre-
quencies (affecting stability in nonvoltage-positioned
circuits). In addition, their relatively low capacitance
value can cause output overshoot when going abruptly
from full-load to no-load conditions, unless the inductor
value can be made small (high switching frequency), or
there are some bulk tantalum or electrolytic capacitors
in parallel to absorb the stored energy in the inductor.
In some cases, there may be no room for electrolytic
capacitors, creating a need for a DC-DC design that
uses nothing but ceramic capacitors.
V
V
0 5
2 97
V
1
s
s
V
V
V
IN MIN
(
)
1 2
.
)
.
.
.
.
.
=
+
μ ×
μ
+
=
0 1
1
0 1
0 1
1 56
V
V
.
2 97
V
1 5
s
s
V
V
V
IN MIN
(
)
1 2
.
)
.
.
.
.
.
=
+
μ ×
μ
+
=
0 5
0 1
1
0 1
0 1
1 74
V
V
V
T
h
K
V
V
IN MIN
(
OUT
DROP
OFF MIN
(
DROP
DROP
)
)
(
)
=
+
×
+
1
2
1
1