17
Maxim Integrated
MAX19792
500MHz to 4000MHz Dual Analog Voltage Variable 
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
the part. In MODE 1, the effective DAC code fed to the 
10-bit DAC register is equal to:
m x Register 1 - n x Register 2
where m and n are the number of UP and DWN control 
steps accumulated, respectively.
After powering up the device, UP and DWN should both 
be set to 0 to reset the m and n counters to 0. This results 
in a 10-bit all 0 code out of the mathematical block in  
Figure  1,  and  applied  to  the  10-bit  DAC  register  that 
drives the DAC. To increase (decrease) the code using 
the UP (DWN) pin, the DWN (UP) pin must be high and 
the UP (DWN) pin should be pulsed low to high. The 
device  is  designed  to  produce  no  wraparounds  when 
using  UP  and  DWN  stepping  so  that  the  DAC  code 
maxes out at 1023 or goes no lower than 0. See Figure 3 
for the UP and DWN control operation.
Switching back to MODE = 0 produces the same 10-bit 
DAC  code  as  was  previously  loaded  into  register  0. 
Switching  back  to  MODE  =  1  results  in  the  previous 
10-bit DAC code from the register 1 and 2 combiner/
multiplier block.
Register 3 is used to set the RDBK_EN register in the 
write mode and is used to read back the RDBK_EN reg-
ister and COMP_OUT in the read mode.
SPI Interface
The device can be controlled with a 4-wire, SPI-compatible 
serial interface. Figure 2 shows a timing diagram for the 
interface. In the write mode, a 13-bit word is loaded into 
the device through the DIN pin, with CS set low. The first 
bit of the word in the write mode is 0, and the next two 
bits select the register to be written to (Table 2). The 
next 10 bits contain the data to be written to the selected 
register. After the 13 bits are shifted in, a low-to-high CS 
command is applied and this latches the 10 bits into the 
selected register. The entire write command is ignored if 
CS is pulsed low to high before the last data bit is suc-
cessfully captured.
For the read cycle, the first bit clocked in is a 1 and this 
establishes that a register is to be read. The next two 
clocked bits form the address of the register to be read 
(Table 2). In this read mode, data starts to get clocked 
out of the DOUT pin after A0 is captured. The DOUT 
pin goes to a high-impedance state after the 10 bits are 
transmitted or if CS goes high at any point during the 
transmission.
Voltage Reference
The device has an on-chip voltage reference for the DAC 
and  a  provision  to  operate  with  an  off-chip  reference. 
Table 6 provides details in selecting the desired reference.
Table 1. Attenuator Control Logic States
DAC_LOGIC
RDBK_EN
(D9, REG 3)
INTERNAL SWITCH 
STATES
ATTENUATOR
10-BIT DAC
0
0
S1 = closed
S2, S3, S4 = open
Controlled by an external analog voltage on the 
CTRL pin.
Disabled
1
0
S1, S3, S4 = open
S2 = closed
Controlled by an on-chip DAC; no voltage is 
applied to the CTRL pin.
Enabled
0
1
S1, S3, S4 = closed
S2 = open
Controlled by an external analog voltage on the 
CTRL
 
pin. CTRL is compared with the  
DAC output. The comparator drives the 
COMP_OUT pin.
Enabled
(update DAC code 
to estimate voltage 
on the CTRL pin)
1
1
S1, S2 = closed
S3, S4 = open
Controlled by an on-chip DAC. The DAC output 
is connected to the CTRL pin. This state can be 
used to test the DAC output. In this condition, 
no voltage can be applied to the CTRL pin and 
the load on this pin must be > 100k&.
Enabled