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參數(shù)資料
| 型號： | MAX19710ETN+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 18/37頁 |
| 文件大小： | 0K |
| 描述： | IC ANLG FRNT END 56-TQFN |
| 產(chǎn)品變化通告： | Product Discontinuation 09/Jun/2011 |
| 標準包裝： | 2,500 |
| 位數(shù)： | 10 |
| 通道數(shù)： | 2 |
| 功率（瓦特）： | 30mW |
| 電壓 - 電源，模擬： | 3V |
| 電壓 - 電源，數(shù)字： | 3V |
| 封裝/外殼： | 56-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 56-TQFN-EP（7x7） |
| 包裝： | 帶卷 (TR) |
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______________________________________________________________________________________
25
MAX19710
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
______________________________________________________________________________________
25
Figure 6. Serial-Interface Timing Diagram
tCSW
tCS
LSB
tCL
tCP
tCH
tDH
tDS
MSB
tCSS
SCLK
DIN
CS/WAKE
QSPI is a trademark of Motorola, Inc.
Figure 7. Mode-Recovery Timing Diagram
CS/WAKE
SCLK
DIN
16-BIT SERIAL DATA INPUT
AD0–AD9
ID/QD
DAC ANALOG OUTPUT
SETTLES TO 10 LSB ERROR
ADC DIGITAL OUTPUT SINAD
SETTLES TO WITHIN 1dB
tWAKE,SD,ST_ TO Rx MODE OR tENABLE,RX
tWAKE,SD,ST_ TO Tx MODE OR tENABLE,TX
= 0, W1 = 0, and W0 = 0. If this value is inadvertently
written to the device, it is ignored and the register con-
tinues to store its previous value. Upon wake-up, the
MAX19710 enters the power mode determined by the
WAKEUP-SEL register, however, all other settings (Tx
DAC offset, Tx DAC common-mode voltage, aux-DAC
settings, aux-ADC state) are restored to their values
prior to shutdown.
The only SPI line that is monitored by the MAX19710
during shutdown is
CS/WAKE. Any information transmit-
ted to the MAX19710 concurrent with the
CS/WAKE
wake-up pulse is ignored.
SPI Timing
The serial digital interface is a standard 3-wire connection
CS/WAKE, SCLK, DIN) compatible with SPI/QSPI/
MICROWIRE/DSP interfaces. Set
CS/WAKE low to enable
the serial data loading at DIN or output at DOUT. Following
a
CS/WAKE high-to-low transition, data is shifted synchro-
nously, most significant bit first, on the rising edge of the
serial clock (SCLK). After 16 bits are loaded into the serial
input register, data is transferred to the latch when
CS/WAKE transitions high. CS/WAKE must transition high
for a minimum of 80ns before the next write sequence.
SCLK can idle either high or low between transitions.
Figure 6 shows the detailed timing diagram of the 3-wire
serial interface.
Mode-Recovery Timing
Figure 7 shows the mode-recovery timing diagram.
tWAKE is the wake-up time when exiting shutdown, idle,
or standby mode and entering Rx, Tx, or FD mode.
tENABLE is the recovery time when switching between
either Rx or Tx mode. tWAKE or tENABLE is the time for
the Rx ADC to settle within 1dB of specified SINAD per-
formance and Tx DAC settling to 10 LSB error. tWAKE
and tENABLE times are measured after the 16-bit serial
command is latched into the MAX19710 by a
CS/WAKE
transition high. In FAST mode, the recovery time is 0.1s
to switch between Tx or Rx modes.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX19710EVCMODU+ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 MAX19710 Eval System RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| MAX19710EVKIT | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| MAX19710EVKIT+ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 MAX19710/13 Eval Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| MAX19711ETN | 功能描述:ADC / DAC多通道 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40 |
| MAX19711ETN+ | 功能描述:ADC / DAC多通道 11Msps CODEC/AFE Full Duplex RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40 |
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