- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄2009 > MAX19705ETM+ (Maxim Integrated Products)IC ANLG FRNT END 48-TQFN PDF資料下載
參數(shù)資料
| 型號： | MAX19705ETM+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 20/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ANLG FRNT END 48-TQFN |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 43 |
| 位數(shù)： | 10 |
| 通道數(shù)： | 4 |
| 功率（瓦特）： | 28.2mW |
| 電壓 - 電源，模擬： | 2.7 V ~ 3.3 V |
| 電壓 - 電源，數(shù)字： | 1.8 V ~ 3.3 V |
| 封裝/外殼： | 48-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 48-TQFN-EP（7x7） |
| 包裝： | 管件 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁
MAX19705
10-Bit, 7.5Msps, Ultra-Low-Power
Analog Front-End
______________________________________________________________________________________
27
12-Bit, Auxiliary Control DACs
The MAX19705 includes three 12-bit aux-DACs (DAC1,
DAC2, DAC3) with 1s settling time for controlling vari-
able-gain amplifier (VGA), automatic gain-control
(AGC), and automatic frequency-control (AFC) func-
tions. The aux-DAC output range is 0.1V to 2.56V.
During power-up, the VGA and AGC outputs (DAC2
and DAC3) are at zero. The AFC DAC (DAC1) is at 1.1V
during power-up. The aux-DACs can be independently
controlled through the SPI bus, except during SHDN
mode where the aux-DACs are turned off completely
and the output voltage is set to zero. In STBY and IDLE
modes the aux-DACs maintain the last value. On wakeup
from SHDN, the aux-DACs resume the last values.
Loading on the aux-DAC outputs should be carefully
observed to achieve specified settling time and stabili-
ty. The capacitive load must be kept to a maximum of
5pF including package and trace capacitance. The
resistive load must be greater than 200k
. If capacitive
loading exceeds 5pF, then add a 10k
resistor in
series with the output. Adding the series resistor helps
drive larger load capacitance (< 15pF) at the expense
of slower settling time.
10-Bit, 333ksps Auxiliary ADC
The MAX19705 integrates a 333ksps, 10-bit aux-ADC
with an input 4:1 multiplexer. In the aux-ADC mode reg-
ister, setting bit AD0 begins a conversion with the auxil-
iary ADC. Bit AD0 automatically clears when the
conversion is complete. Setting or clearing AD0 during
a conversion has no effect (see Table 11). Bit AD1
determines the internal reference of the auxiliary ADC
(see Table 12). Bits AD2 and AD3 determine the auxil-
iary ADC input source (see Table 13). Bits AD4, AD5,
and AD6 select the number of averages taken when a
single start-convert command is given. The conversion
time increases as the number of averages increases
(see Table 14). The conversion clock can be divided
down from the system clock by properly setting bits
AD7, AD8, and AD9 (see Table 15). The aux-ADC out-
put data can be written out of DOUT by setting bit
AD10 high (see Table 16).
The aux-ADC features a 4:1 input multiplexer to allow
measurements on four input sources. The input sources
are selected by AD3 and AD2 (see Table 13). Two of
the multiplexer inputs (ADC1 and ADC2) can be con-
nected to external sources such as an RF power detec-
tor like the MAX2208 or temperature sensor like the
MAX6613. The other two multiplexer inputs are internal
connections to VDD and OVDD that monitor the power-
supply voltages. The internal VDD and OVDD connec-
tions are made through integrated resistor-dividers that
yield VDD / 2 and OVDD / 2 measurement results. The
aux-ADC voltage reference can be selected between
an internal 2.048V bandgap reference or VDD (see
Table 12). The VDD reference selection is provided to
allow measurement of an external voltage source with a
full-scale range extending beyond the 2.048V level. The
input source voltage range cannot extend above VDD.
Table 11. Auxiliary ADC Convert
Table 12. Auxiliary ADC Reference
Table 13. Auxiliary ADC Input Source
AD0
SELECTION
0
Aux-ADC Idle (Default)
1
Aux-ADC Start-Convert
AD1
SELECTION
0Internal 2.048V Reference (Default)
1
Internal VDD Reference
AD3
AD2
AUX-ADC INPUT SOURCE
00
ADC1 (Default)
01
ADC2
10
VDD / 2
11
OVDD / 2
相關PDF資料 |
PDF描述 |
|---|---|
| MAX19706ETM+T | IC ANLG FRNT END 48-TQFN |
| MAX19707ETM+T | IC ANLG FRNT END 48-TQFN |
| MAX19708ETM+ | IC ANLG FRONT END 11MSPS 48-TQFN |
| MAX19710ETN+T | IC ANLG FRNT END 56-TQFN |
| MAX19711ETN+T | IC ANLG FRNT END 56-TQFN |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX19705ETM+ | 功能描述:ADC / DAC多通道 7.5Msps CODEC/AFE 1.8/2.7-3.3V RoHS:否 制造商:Texas Instruments 轉換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-40 |
| MAX19705ETM+GH7 | 功能描述:ADC / DAC多通道 10-Bit 7.5Msps Ultra-Low-Power Analog Front-End RoHS:否 制造商:Texas Instruments 轉換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-40 |
| MAX19705ETM+T | 功能描述:ADC / DAC多通道 7.5Msps CODEC/AFE 1.8/2.7-3.3V RoHS:否 制造商:Texas Instruments 轉換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-40 |
| MAX19705ETM+TGH7 | 功能描述:ADC / DAC多通道 10-bit 7.5Msps Ultra-Low-Power Analog Front-End RoHS:否 制造商:Texas Instruments 轉換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-40 |
| MAX19705ETM-T | 功能描述:ADC / DAC多通道 RoHS:否 制造商:Texas Instruments 轉換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-40 |
發(fā)布緊急采購，3分鐘左右您將得到回復。