參數(shù)資料
型號(hào): MAX195BEWE+T
廠商: Maxim Integrated Products
文件頁數(shù): 27/28頁
文件大?。?/td> 0K
描述: IC ADC 16BIT 85KSPS 16-SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1,000
位數(shù): 16
采樣率(每秒): 85k
數(shù)據(jù)接口: QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 80mW
電壓電源: 模擬和數(shù)字,雙 ±
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC W
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個(gè)單端,單極;1 個(gè)單端,雙極
MAX195
after the end of the previous conversion and EOC will
go high on the following CLK falling edge (Figure 4).
External Clock
The conversion clock (CLK) should have a duty cycle
between 25% and 75% at 1.7MHz (the maximum clock
frequency). For lower frequency clocks, ensure the min-
imum high and low times exceed 150ns. The minimum
clock rate for accurate conversion is 125Hz for temper-
atures up to +70°C or 1kHz at +125°C due to leakage
of the sampling capacitor array. In addition, CLK
should not remain high longer than 50ms at tempera-
tures up to +70°C or 500s at +125°C. If CLK is held
high longer than this, RESET must be pulsed low to initi-
ate a recalibration because it is possible that state
information stored in internal dynamic memory may be
lost. The MAX195’s clock can be stopped indefinitely if
it is held low.
If the frequency, duty cycle, or other aspects of the
clock signal’s shape change, the offset created by cou-
pling between CLK and the analog inputs (AIN and
REF) changes. Recalibration corrects for this offset and
restores DC accuracy.
Output Data
The conversion result, clocked out MSB first, is avail-
able on DOUT only when CS is held low. Otherwise,
DOUT is in a high-impedance state. There are two ways
to read the data on DOUT. To read the data bits as they
are determined (at the CLK clock rate), hold CS low
during the conversion. To read results between conver-
sions, hold CS low and clock SCLK at up to 5MHz.
If you read the serial data bits as they are determined,
EOC frames the data bits (Figure 6). Conversion begins
with the first falling CLK edge, after CONV goes low
and the input signal has been acquired. Data bits are
shifted out of DOUT on subsequent falling CLK edges.
Clock data in on CLK’s rising edge or, if the clock
speed is greater than 1MHz, on the following falling
edge of CLK to meet the maximum CLK-to-DOUT tim-
ing specification. See the
Operating Modes and
SPI/QSPI Interfaces section for additional informa-
tion. Reading the serial data during the conversion
results in the maximum conversion throughput,
because a new conversion can begin immediately after
the input acquisition period following the previous con-
version.
16-Bit, 85ksps ADC with 10A Shutdown
8
_______________________________________________________________________________________
TRACK/HOLD
CLK
CONVERSION
BEGINS
CONVERSION
ENDS
tAQ
*
* THE FALLING EDGE OF CONV MUST OCCUR IN THIS REGION
tCEL
tCW
tCEH
tCC2
tCC1
EOC
CONV
Figure 4. Initiating Conversions—Less than 3 CLK cycles since end of previous conversion.
SPI/QSPI are trademarks of Motorola Corp.
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