參數(shù)資料
型號: MAX19516ETM+T
廠商: Maxim Integrated Products
文件頁數(shù): 17/35頁
文件大?。?/td> 0K
描述: IC ADC 10BIT 2CH 100MSPS 48TQFN
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
位數(shù): 10
采樣率(每秒): 100M
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-WFQFN 裸露焊盤
供應商設備封裝: 48-TQFN-EP(7x7)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 4 個單端,單極;2 個差分,單極
Clock Inputs
The input clock interface provides for flexibility in the
requirements of the clock driver. The MAX19516
accepts a fully differential clock or single-ended logic-
level clock. For differential clock operation, connect a
differential clock to the CLK+ and CLK- inputs. In this
mode, the input common mode is established internally
to allow for AC-coupling. The differential clock signal
can also be DC-coupled if the common mode is con-
strained to the specified 1V to 1.4V clock input com-
mon-mode range. For single-ended operation, connect
CLK- to GND and drive the CLK+ input with a logic-
level signal. When the CLK- input is grounded (or
pulled below the threshold of the clock mode detection
comparator) the differential-to-single-ended conversion
stage is disabled and the logic-level inverter path is
activated.
Clock Divider
The MAX19516 offers a clock-divider option. Enable
clock division either by setting DIV0 and DIV1 through
the serial interface; see the Clock Divide/Data
MAX19516
Dual-Channel, 10-Bit, 100Msps ADC
24
______________________________________________________________________________________
Figure 8. Simplified Clock Input Schematic
DCLK
DATA, DOR
SAMPLE CLOCK
n
n+1
SAMPLE ON RISING EDGE
n+2
n+4
n+5
n-9
n-8
n-10
n-7
n-6
n-5
n-4
tCLK
tSETUP
tCH
tDD
tDC
tHOLD
tCL
DUAL-BUS OUTPUT MODE
SAMPLE CLOCK IS THE DERIVED CLOCK FROM (CLK+ - CLK-)/CLOCK DIVIDER, IN_ = IN_+ - IN_-.
SAMPLING
INSTANT
SAMPLING
INSTANT
SAMPLING
INSTANT
SAMPLING
INSTANT
SAMPLING
INSTANT
SAMPLING
INSTANT
IN_
tAD
n+3
Figure 9. Dual-Bus Output Mode Timing
CLK+
100
TERMINATION
(PROGRAMMABLE)
SELF-BIAS TURNED OFF FOR
SINGLE-ENDED CLOCK
OR POWER-DOWN.
CLK-
GND
AVDD
10k
20k
5k
5k
50
50
2:1 MUX
SELECT
THRESHOLD
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