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參數(shù)資料
| 型號： | MAX19506ETM+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 18/35頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT 2CH 100MSPS 48TQFN |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 43 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 100M |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 139mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 48-TQFN-EP（7x7） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 4 個單端，單極；2 個差分，單極 |
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MAX19506
Dual-Channel, 8-Bit, 100Msps ADC
______________________________________________________________________________________
25
Format/Test Pattern register (06h) for clock-divider
options, or in parallel programming configuration (SPEN
= 1) by using the DIV input.
System Timing Requirements
Figures 9 and 10 depict the relationship between the
clock input and output, analog input, sampling event,
and data output. The MAX19506 samples on the rising
edge of the sampling clock. Output data is valid on the
next rising edge of DCLK after a nine-clock internal
latency. For applications where the clock is divided, the
sample clock is the divided internal clock derived from:
[(CLK+ - CLK-)/DIVIDER]
Synchronization
When using the clock divider, the phase of the internal
clock can be different than that of the FPGA, microcon-
troller, or other MAX19506s in the system. There are
two mechanisms to synchronize the internal clock: slip
synchronization and edge synchronization. Select the
synchronization mode using SYNC_MODE (bit 2) in the
Clock Divide/Data Format/Test Pattern register (06h)
and drive the SYNC input high to synchronize.
Slip Synchronization Mode, SYNC_MODE = 0
(default): On the third rising edge of the input clock
(CLK) after the rising edge of SYNC (provided set-up
and hold times are met), the divided output is forced to
skip a state transition (Figure 11).
Edge Synchronization Mode, SYNC_MODE = 1: On
the third rising edge of the input clock (CLK) after the
rising edge of SYNC (provided set-up and hold times
are met), the divided output is forced to state 0. A divid-
ed clock rising edge occurs on the fourth (/2 mode) or
fifth (/4 mode) rising edge of CLK, after a valid rising
edge of SYNC (Figure 12).
DCLK
DATA, DOR
SAMPLE CLOCK
n-9
CHA
CHB
n-9
n-8
CHA
CHB
n-8
CHB
n-10
n-7
CHA
CHB
n-7
n-6
CHA
CHB
n-6
n-5
CHA
CHB
n-5
n-4
CHA
CHB
n-4
MUX OUTPUT MODE
IN_
SAMPLING
INSTANT
SAMPLING
INSTANT
SAMPLING
INSTANT
SAMPLING
INSTANT
SAMPLING
INSTANT
SAMPLING
INSTANT
tAD
n
n+1
n+2
n+4
n+5
n+3
tCH
tCL
SAMPLE ON RISING EDGE
tDC
tDD
tCHA
tDCH
tSETUP
tHOLD
tDCL
tSETUP
tCHB
SAMPLE CLOCK IS THE DERIVED CLOCK FROM (CLK+ - CLK-)/CLOCK DIVIDER, IN_ = IN_+ - IN_-.
MUX_CH (BIT 2, OUTPUT FORMAT 01h) DETERMINES THE OUTPUT BUS AND WHICH CHANNEL DATA IS PRESENTED.
tCLK
Figure 10. Multiplexed Output Mode Timing
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX19506ETM+ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8-Bit 2Ch 100Msps 1.8V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構:Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX19506ETM+T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8-Bit 2Ch 100Msps 1.8V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構:Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX19506EVKIT+ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 MAX19505-07/15-17 Eval Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| MAX19507ETM+ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8-Bit 2Ch 130Msps 1.8V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構:Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX19507ETM+T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8-Bit 2Ch 130Msps 1.8V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構:Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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