參數(shù)資料
型號: MAX19505EVKIT+
廠商: Maxim Integrated Products
文件頁數(shù): 4/35頁
文件大?。?/td> 0K
描述: KIT EVALUATION FOR MAX1950 ADC
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1
ADC 的數(shù)量: 2
位數(shù): 8
采樣率(每秒): 65M
數(shù)據(jù)接口: 串行,并聯(lián)
輸入范圍: 0.4 ~ 1.4 V
在以下條件下的電源(標準): 43mW @ 65MSPS,1.8V
工作溫度: -40°C ~ 85°C
已用 IC / 零件: MAX19505
已供物品: 板,軟件
MAX19505
Dual-Channel, 8-Bit, 65Msps ADC
12
______________________________________________________________________________________
Pin Description
PIN
NAME
FUNCTION
1, 12, 13, 48
AVDD
Analog Supply Voltage. Bypass each AVDD input pair (1, 48) and (12, 13) to GND with 0.1F.
2
CMA
Channel A Common-Mode Input-Voltage Reference
3
INA+
Channel A Positive Analog Input
4
INA-
Channel A Negative Analog Input
5
SPEN
Active-Low SPI Enable. Drive high to enable parallel programming mode.
6
REFIO
Reference Input/Output. To use internal reference, bypass to GND with a > 0.1F capacitor. See
the Reference Input/Output (REFIO) section for external reference adjustment.
7
SHDN
Active-High Power-Down. If
SPEN is high (parallel programming mode), a register reset is initiated
on the falling edge of SHDN.
8
I.C.
Internally Connected. Leave unconnected.
9
INB+
Channel B Positive Analog Input
10
INB-
Channel B Negative Analog Input
11
CMB
Channel B Common-Mode Input-Voltage Reference
14
SYNC
Clock-Divider Mode Synchronization Input
15
CLK+
Clock Positive Input
16
CLK-
Clock Negative Input. If CLK- is connected to ground, CLK+ is a single-ended logic-level clock
input. Otherwise, CLK+/CLK- are self-biased differential clock inputs.
17, 18
GND
Ground. Connect all ground inputs and EP (exposed pad) together.
19
DORB
Channel B Data Over Range
20
DCLKB
Channel B Data Clock
21
I.C.
Internally Connected. Leave unconnected.
22
I.C.
Internally Connected. Leave unconnected.
23
D0B
Channel B Three-State Digital Output, Bit 0 (LSB)
24
D1B
Channel B Three-State Digital Output, Bit 1
25, 36
OVDD
Digital Supply Voltage. Bypass each OVDD input to GND with 0.1F capacitor.
26
D2B
Channel B Three-State Digital Output, Bit 2
27
D3B
Channel B Three-State Digital Output, Bit 3
28
D4B
Channel B Three-State Digital Output, Bit 4
29
D5B
Channel B Three-State Digital Output, Bit 5
30
D6B
Channel B Three-State Digital Output, Bit 6
31
D7B
Channel B Three-State Digital Output, Bit 7 (MSB)
32, 33
I.C.
Internally Connected. Leave unconnected.
34
D0A
Channel A Three-State Digital Output, Bit 0 (LSB)
35
D1A
Channel A Three-State Digital Output, Bit 1
37
D2A
Channel A Three-State Digital Output, Bit 2
38
D3A
Channel A Three-State Digital Output, Bit 3
39
D4A
Channel A Three-State Digital Output, Bit 4
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